Overview

The Aldec DO-254 Compliance Tool Set (CTS) provides support for the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED80) Chapter 6.2 “Verification Process” and Chapter 11.4 “Tool Assessment and Qualification Process”. The Aldec DO-254 CTS supports a fast and reliable verification process for assurance levels A-D with a focus on increased coverage, testability, and visibility in hardware together with design requirements traceability.

The Challenge

Verifying FPGA, PLD, and ASIC designs in hardware, while tracing the output results back to the original design requirements, is a significant challenge with today’s DO-254 verification solutions. With HDL simulation, it is possible to comprehensively simulate the entire design with an exhaustive testbench. With in-hardware testing however, it is difficult to achieve a similar level of verification. Typically, traditional hardware testing methods with a logic analyzer allow for examining only a small portion of the design logic in the target device on the system board. Checking corner-stone cases can be challenging because they require manipulating the real I/O data from the target device. Usually only a small percentage of the device I/O pins are accessible on the final system board, limiting the testability of the device. But with the Aldec DO-254 CTS, all of the I/O pins are available, allowing the whole design to be verified in the target device. Traditional in-hardware testing, with all of its limitations, is not adequate to fulfill the verification process of the DO-254 specification for Level A and B compliance; these levels require catastrophic failure analysis of the design in the target hardware device.

Introduction

Designing hardware for DO-254 compliance presents unique challenges, and designers are increasingly turning to the solutions offered by the Aldec DO-254 CTS to overcome these challenges. The DO-254 CTS consists of a simulation tool suite combined with advanced hardware to provide comprehensive verification of FPGA, PLD, and ASIC designs from the Hardware Description Language (HDL) level to the hardware device. The advantage of the Aldec DO-254 CTS is the ability to test the design at-speed in the actual hardware with the same flexibility, traceability and coverage as during functional HDL simulation. Typically, traditional hardware testing methods with a logic analyzer allow for testing only a small portion of the design logic in the hardware. But with the Aldec DO-254 CTS, the testbench used for HDL simulation can be reused for In-Hardware testing, achieving the desired 100% functional coverage, this time in the actual target device. Aldec’s solution is based on its patented Hardware Emulation System technology (U.S. Patent 5,479,355).

The DO-254 Standard

The airborne electronic hardware development guidance document (RTCA DO-254/EUROCAE ED-80) is the counterpart to the well-established civil avionics software standard (RTCA DO-178B/EUROCAE ED-12B). The DO-254 standard provides a guide to the development of designs for complex electronic hardware in avionics. Complex electronic hardware includes devices such as FPGAs, PLDs, and ASICs. The sections of the DO-254 specification addressed by the Aldec DO-254 CTS are the Verification Process (Chapter 6.2) and the Tool Assessment and Qualification Process (Chapter 11.4). In Figure 1 below, the basic flow of the DO-254 compliance verification process is presented, from the Requirements Capture Process all the way through In-Hardware Testing. For more information on the DO-254 standard, go to www.aldec.com, www.do254.com, and www.highrely.com.

Figure 1: DO-254 Compliance Verification Process

The Design Verification Process with the Aldec DO-254 CTS

The Aldec DO-254 CTS provides support for each stage of the verification process, as shown in Figure 2 below. The design process begins with defining the requirements allocated to the hardware, and then writing HDL code to meet the requirements. Once the HDL code is complete and compiled into a design, HDL simulation can verify that the design functions correctly and does not produce any unexpected outcomes. An exhaustive testbench needs to be created for use with the HDL simulator. For complex designs, testbenches are often supplemented with advanced verification techniques, like SystemC™, SystemVerilog, assertions-based verification, and constrained-random stimulus generation; all of these advanced methods are supported by Aldec’s HDL simulators.

To determine how much of the design is being exercised by the testbench, the designer can use several metrics to measure the coverage. These metrics include code, structural, and functional coverage, along with assertion or checker density. Generating a thorough testbench with 100% functional coverage can be a lengthy process, and unfortunately, most verification tools do not reuse this testbench for later stages of testing. An advantage of the Aldec DO-254 CTS is that it uses the HDL testbench with 100% functional coverage for In-Hardware testing.

Figure 2: Design and Verification Stages with the Aldec DO-254 CTS

Following functional simulation of the HDL code, the design can be synthesized. After synthesis, the design netlist will be routed by the P&R tool. Once the design has been routed, the designer can program the actual FPGA (or PLD) device with the bit file generated by the P&R tool. At this point, In-Hardware testing can begin. Typically, a logic analyzer or other test equipment is used to verify the design in the target hardware, Aldec DO254 CTS with test headers placed on the system board for easy connection to standard logic analyzer test connectors. The designer is then able to monitor some of the I/O pins on the hardware device directly from the logic analyzer. This traditional approach to In-Hardware testing works reasonably well to identify expected bugs and verify small sections of the hardware design. However, it is an impractical and inefficient method of testing when the purpose is verification of the entire design for DO-254 compliance. When a conventional check is performed on the production board, it is difficult to check all of the testing requirements including corner-stone cases because they require manipulating the real I/O data from the target device. Usually only a small percentage of the device I/O pins are accessible on the final system board, limiting the testability of the device. But with the Aldec DO-254 CTS, all of the I/O pins are available, allowing the whole design to be verified in the target device.

Traditional In-Hardware testing, with all of its limitations, is not adequate to fulfill the verification process of the DO-254 specification for Level A and B compliance; these levels require catastrophic failure analysis of the design in the target hardware device. Generating documentation, coverage metrics, and traceability of the hardware outputs back to the requirements are all challenging issues with traditional In-Hardware testing. In addition to these challenges, the design team is usually required to start from scratch to create a new test method for In-Hardware testing. A better way to test the design in hardware is to reuse the HDL testbench with 100% functional coverage to comprehensively test the target device.

Benefits of the Aldec DO-254 CTS

• Same number of tests can be run in the target device as in the HDL simulator; 100% functional coverage can be easily assured and automatically implemented.
• Full design verification in the target device can be made before a system test.
• The verification process runs at speed, driven by the vectors captured during HDL simulation.
• Automatic results comparison between the HDL simulation and In-Hardware testing.
• Automatic documentation and traceability of In-Hardware testing results back to the design requirements.

With the Aldec DO-254 CTS, the designer is able to reuse the same testbench from HDL simulation for In-Hardware testing. The results from In-Hardware testing are recorded in software and can be viewed in the standard waveform format. Also, using the Compare Waveforms function of the Aldec simulator, the designer can automatically compare In-Hardware test waveforms to the HDL simulation waveforms, quickly spotting any discrepancies. For example, the golden set of waveform vectors validated in the HDL simulation can be compared with the set of waveform vectors generated in the target device. Providing evidence of verification is simple with the automatic documentation feature of Aldec’s HDL simulators; this feature allows the designer to easily document the recorded outputs from the FPGA, PLD or ASIC device. These recorded outputs from the hardware device also provide traceability back to the design requirements. In-Hardware testing at-speed with 100% functional coverage verifies the design in the actual hardware device, completing the design verification cycle for DO-254.

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May 1, 2008

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