Pin and part swapping has long been one of the many techniques that electronics designers exploit to decrease PCB routing complexity and remain competitive. But the accelerated adoption of FPGAs due to their increased affordability and ever-improving performance has placed new pressures on traditional PCB design flows.

Yesterday's task of exchanging a few gates within an IC package or the connections to a couple of resistor arrays is quite different from today's task of managing several hundred pin swaps across one or more FPGA devices, and then synchronizing those changes with the FPGA design. As the design progresses through multiple iterations, the task of synchronizing the data and pins across the PCB and FPGA domains has become a full-time job in itself and the blessing of pin swapping has become a curse.

So, designers need to overcome this increasing synchronization complexity so that they can continue to exploit the benefits of programmable hardware.

Through examining traditional design processes and their efficiency at dealing with FPGA-based designs, this paper explores the ways that board level designers can harness the benefits of FPGAs without being overwhelmed by their complexity. Of particular interest is the management of pin swapping data across schematic, PCB and FPGA design domains.

I'll examine the various synchronization techniques that are typically used by board level designers to synchronize their schematic and PCB design data, and how those techniques need to change to deal with the complexities introduced by increasingly more powerful FPGAs. I'll propose an improved data synchronization model along with some key considerations that need to be kept in mind when purchasing a design tool.

The old and the new: design synchronization the old way

The design of custom board-level products has typically consisted of two primary phases; schematic capture and PCB layout. Schematics are created first as a logical representation of the circuit. They use the language of symbols and circuit topologies to communicate both design intent and the connectivity model. The PCB layout process takes this connectivity model and seeks to create a physical representation of the design that can be manufactured reliably and economically.

One of the challenges of working between the schematic and PCB environments is that whilst the schematic document is responsible for specifying the logical connections between components, it is not until the design is migrated into the PCB layout tool that physical optimization opportunities become apparent. For example, where multiple components exist within a single package such as in a resistor array, the schematic developer may have wired up the resistors indiscriminately but the PCB layout specialist may wish to reorder the connections to improve track placement.

As the design evolves and the connection model is updated, any change made in either the schematic or PCB domain needs to be propagated through to the other domain to ensure project level synchronization. There are two ways that this is typically done. Older design packages (or design packages caught in an old paradigm of design) only support the forward propagation of design information from the schematic to the PCB. In this instance the only reliable way to make changes to PCB connections is to modify the schematic documents and then propagate those changes through. For simple designs this is little more than a small inconvenience but for larger designs, or more complex designs, or for designs requiring the in-built flexibility and advantages of FPGAs, the inconvenience can become large.

The limitations of forward-only data synchronization quickly become apparent when trying to perform pin or part swapping at the PCB level. This is often an iterative process since changes made to one device or set of connections will often reveal, and lead to, further optimization opportunities. If forward propagation is the only means for design synchronization, designers may find themselves going round the 'modify schematic, update PCB' cycle many times over. Each time through the design loop consumes time, which over several iterations can be substantial.

Ideally, the process of improving track routing should be a less arduous task driven from the PCB layout tool. This makes a lot more sense given that it is the layout expert who is directing the changes. But for this to be possible, the design system must support the propagation of design information from the layout tool back to the schematic tool. This can be accomplished through an Engineering Change Order (ECO) process or a 'was/is' file. After performing various updates to the PCB document, an ECO file is created and passed to the schematic tool for incorporation into the schematic sheets. This file is sometimes called a was/is file because of the way the updates are ordered within it; i.e. pin 1 was connected to pin 2, pin 1 is now connected to pin 3.

The use of ECO files is an intuitive process but it relies on the user following strict design processes. If more than one ECO file is generated through the life of the project, extreme caution needs to be exercised to ensure it is applied to the schematic in the exact order it was created. If manual edits are applied to the schematic before the ECO files have been incorporated, then synchronization can be totally defeated and the design edits lost. Recovering from such a situation can mean many hours of mind-numbing tedium.

Figure 1. As the pin count goes up, the cost of manually pin swapping FPGA devices increases significantly.

Designing without adequate synchronization tools is painful

The ECO method is the most common means of design synchronization in schematic and PCB design systems. But unfortunately, most tool vendors treat the FPGA design process as being separate from the board level design process. So the ECO process that is integral to the synchronization of schematic and PCB documents does not extend to FPGA design data.

Overcoming this data disconnect can be a particularly painful experience when resorting to manual means. Whilst it may be feasible to manually synchronise PCB, schematic and FPGA design data for very small FPGA devices, the thought of having to do this across an FPGA device with 1000+ pins can be totally demoralizing. As an example, consider a 1000 pin device that is iteratively pin swapped 10 times in an effort to improve the routing complexity and PCB layout options. This relates to a total of 10,000 pins requiring manual check and synchronization. Assuming it takes approximately 1 minute to check and update each pin, the total time consumed through pin swapping alone would be 10,000 minutes or 166 hours. At a nominal cost of $50 per hour, the cost of this activity translates to over $8300 in labour costs and a delay of around one month in the development plan. (See Figure 1)

As an alternative to manual pin and data synchronization, several design tool vendors offer various add-ons which, together with their core products, form an 'integrated' solution. In proposing this, they view the propagation of FPGA data into board-level design processes as little more than an incremental change to existing processes. But it is a view that needs to be challenged.

Integrated tools consider electronics design to be a sequence of disparate design processes and the design data is localized to the process that creates it. Where data from one process is required by another process, it is made available through a separate 'bolt-on' utility that is responsible for parsing the data into the appropriate downstream format. Upstream data propagation, if available, is managed through another utility that performs the backwards conversion.

On the surface, purchasing add-ons to an existing design package may appear to be a good solution but a more detailed analysis reveals that it introduces considerable complexity to the overall design process. Because design data is stored locally to the processes that use it, data synchronization problems can actually compound rather than improve. (See Figure 2)

Figure 2. Using a 'bolt-on' module or utility to manage FPGA data in a PCB design. Note the added complexity that is added to the design flow.

The old and the new: making pin and part swapping in FPGA designs a new, profitable reality

Given the apparent complexity and cost of managing pin swaps across designs that incorporate FPGAs, one option would be to admit defeat and retreat to the position of disallowing all pin swaps whatsoever. But that would forfeit one of the key benefits of using FPGAs.

On any non-programmable device, the high number of pins can create routing headaches but the exact opposite can be true of FPGAs. Having the ability to quickly and easily change the pins on which IO signals emerge from can have a dramatic improvement on the board layout and actually lead to a drop in the number of layers and complexity of the PCB. By using the programmable nature of the FPGA, much of the PCB routing challenge can be pushed inside the FPGA where it can be handled by automated tools.

So for designers to remain competitive while still holding onto their sanity, they need design tools that understand the challenges posed by pin swapping and synchronizing large-scale FPGA devices. They need a design approach that is in tune with the combined needs of FPGA and PCB development. They need an alternate approach to design that goes beyond existing methods.

In creating such a system, there are a number of features that it would need to offer. For example, existing design approaches effectively require the PCB layout expert to be familiar with the specifics of the FPGA design. This may be a reasonable expectation for non-configurable devices but the very fact that FPGA internals can be programmed means that the exact function of each of the pins will vary according to the application. It will therefore be impossible for the PCB layout expert to know which pins can and cannot be swapped purely from looking at the component's datasheet or pin out.

Figure 3. Using the properties of the targeted FPGA device to assist with creating pin swapping rules.

Figure 4. One approach to propagating pin swapping information between FPGA and PCB documents.

An alternate design system should empower the PCB layout expert to perform pin swapping without being expected to know the specifics of the FPGA design. Instead, the FPGA designer would specify which pins can and cannot be swapped and then embed that information into the design data. The PCB layout expert can then treat the FPGA as a virtual black box and use the embedded rules to guide any pin swapping that is necessary.

As this approach would require co-operation from the FPGA designer to input the relevant pin swapping rules, some assistance should be offered for this task. A mixture of information derived directly from the target FPGA device such as IO standards, IO banks, drive strength, signal names, etc, could all be used to help the FPGA designer quickly create the necessary pin swapping rules.
(See Figure 3)

Since pin swapping at the PCB level is largely a process of minimizing trace lengths and cross-overs, once the pin swapping rules have been defined, the actual process of performing the swaps could be readily solved automatically. Of course there will always be the need for some human interaction but on the whole, an automated pin swapping process would be desirable.

Finally, once pin swaps have been made, there remains the need to seamlessly propagate the relevant changes into the FPGA design where it can be checked and verified before final approval is granted. (See Figure 4) Should timing or some other constraint be violated, the design tool should allow for further constraint information to be given back to the PCB designer so that it can be incorporated into additional updates.

What to consider when selecting a design tool

Having embraced FPGAs and the opportunities they bring to electronics product development, design organizations need a design tool that goes beyond old design methods and offers improved ways to manage the growing complexity of high pin-count FPGAs. It is no longer sufficient to treat the board design and layout processes as being separate from the FPGA design process. Whilst they might be performed by different people, they are ultimately all part of a bigger product development process and need to be linked as such.

A better design tool is one that operates on the design in its entirety and uses a data model that is capable of encompassing all of its facets. In short, the design of one product's electronics should be serviced by a single, unified design system.

Unified design tools have a fundamentally different view of the design process and the data on which it operates. Because they treat electronics design as a single, all-encompassing design process, they use a much more centralized design data model that accommodates all aspects of the FPGA device including its electrical, functional, and physical characteristics. This model goes beyond an integration model because it refuses to treat the process of design as being a sequence of disparate and isolated processes. Instead, it provides:

• A single design process for all aspects of development
• A single coherent 'model' of the design
• A single coherent 'model' of the components used.

In this model, a unified design system also provides:

• A single design application with a single user interface
• A single design data storage model

Pertinent design information is centrally accessed and can be used across any of the design activities that might benefit from it. Design data entered by the FPGA designer is automatically made available to the PCB designer and vice-versa. Data propagation is greatly simplified since it does not require management across multiple disparate processes. (See Figure 5)

Figure 5. Compare to Figure 2. Choosing a unified design tool with a unified data storage. Approach simplifies the entire design process, including pin swapping.

A unified design system relieves designers from managing the tedium of complex data synchronization and lets them focus on developing the core features of the product. This is a far more profitable endeavour given that it is those features that will provide the product with its market differentiation, and it is the speed at which the product gets to the market that will drive its market share and ultimate profits.

When compared with manual pin swapping and synchronization processes, a unified design tool can bring considerable savings. For low pin-count devices, the savings are modest but as the pin-count increases, the savings become much more substantial.

Figure 6. Savings resulting from using a unified design tool are equal to the cost of manual pin swapping and synchronization less the time required to setup pin swap rules.

For example, on a very high pin-count device with 1760 pins, the FPGA designer may take up to 1 hour to completely specify the pin swapping rules. But once that is done, pin swapping along with any data synchronization can be fully automated. The savings can extend into several tens of thousands of dollars. (See Figure 6)

As this graph demonstrates, the costs of manually pin swapping high pin-count devices continue to increase. But with a unified design tool, the only 'cost' is in the setup of pin swapping rules. After that has been done, pin swaps can be automated and synchronized without any additional time or cost to the design, ultimately saving more each time there is a design iteration.

The proliferation of FPGAs will continue to increase over the coming years and the management of their complexity will stand as a major obstacle to companies that do not invest in the right design tools. Design unification should be a key consideration when making any purchasing decision.

Conclusion

The emergence of FPGAs into the mainstream of electronics product development brings many opportunities. There remain good commercial and design benefits associated with the use of FPGA devices, and the execution and synchronization of pin swapping data across schematic, PCB and FPGA design centres must be carefully managed to tap these benefits.

Traditional design synchronization models treat board-level and FPGA design activities as disparate processes and do not adequately deal with the complexity of high pin-count FPGAs. As a result, they sap time and resources away from the core product development efforts and can cost companies dearly in lost market opportunities and profits.

The unified data model along with an associated unified design tool is the best solution for managing the complexity and challenges presented by FPGAs. It encapsulates all aspects of the design into a single, coherent model that can be worked on from within a single design application. By centralizing the design process, design data such as pin swapping information can be captured and synchronized more efficiently and seamlessly across the PCB and FPGA domains, allowing time to be spent focusing on the higher value design areas.

FPGAs are offering many opportunities to companies engaged in the development of new and exciting electronic products. Given a unified electronics design tool, it is possible to overcome the increasing management complexity of developing with modern FPGA devices and harness their benefits.

Marty Hauff, B. Eng. (Computer and Digital Systems) Manager, Altium Designer Applied Technologies

March 20, 2008

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