Summary

Digital displays are a fast-growing market comprising LCD, plasma, and rear projection television technologies as well as smaller displays for mobile handsets and automobiles, in addition to many other applications. Digital image processing enhances the overall viewing aesthetics of the displayed image and can differentiate your product.

Xilinx has developed a reference design IP core based on the Xilinx Spartan™-3E Display Development Board and intended for display panel applications to assist in developing products for this market. The display solution FPGA consists of a DVI Input interface, color temperature correction, precise gamma correction, an image dithering engine, and Low-Voltage Differential Signaling (LVDS) Transmit (TX) or DVI TX output interface (see Figure 1).

This document describes the Spartan-3E Display Development Board. It also provides details on the DIP switch settings and detailed resource counts for each of the IP blocks.

Figure 1: Xilinx Display Panel IP Reference Design Flow

Table 1 defines the key IP blocks in the Spartan-3E Display Development Board.

Table 1: IP Block Descriptions

User Switch and Push Button Settings

The switch settings in this document refer to the User Set DIP Switch block on the Spartan-3E Display Development Board (see Figure 2).

Figure 2: Display Development Board Switch Settings

Table 2: User DIP Switch Settings

The image dithering engine is modified using the user push button settings:

• "0": used when the push button is depressed
• "1": used when the push button is released

DVI Receiver (RX) Interface Block

The DVI RX interface must be used for this reference design. Refer to the Display Development Board User Guide to set up the DVI option. Table 3 shows the DIP switch settings to configure the DVI RX interface.

Table 3: LVDS DIP Switch Settings for LVDS/DVI RX Selection

Introduction to Color Temperature

White light can be described by color temperature. To determine the color temperature of a light source, its output is compared with a theoretical "black-body radiator" at a certain temperature in Kelvin. Specifically, 5000K to 5500K is seen in typical daylight, 2000K is red/orange, and 15000K is bluish. Different light sources and different display technologies show differing color temperatures. For example, as the sun crosses the sky, it may appear to be red, orange, white, or blue, depending on its position.

In digital displays, white color is realized by a superposition of the R, G, and B color emitted from the R, G, and B cells of the specific display. RGB data can be transformed to fit the CIE x-y color space, the color space where many calculations are performed in this algorithm.

The term "White Point" is loosely defined as color temperature. On a CIE chromaticity diagram (Figure 3), a white point at 5500K is near the point x = y = 0.33.

Figure 3: Color Temperature on CIE Chromaticity Diagram

For example, plasma display panels (PDPs) show a low color temperature, especially compared to a conventional cathode ray tube (CRT) display. The low color temperature of the PDP is caused by an inherent low blue luminance. Furthermore, the end customer cannot arbitrarily vary the color temperature once the PDP cell structure and the related driving scheme are fixed. A digital display output such as a PDP must be color corrected to achieve better image quality.

CTC Algorithm

In this algorithm implementation, the white point or color temperature of the frame is changed to the desired color temperature of that particular frame. First, a CIE reference white point is selected in x and y format from a user-selected temperature input. For every incoming frame, a white point is estimated. The input frame of the 8- or 10-bit RGB data is converted into x-y format using a color-mixing program.

Next, the incoming frame temperature and the reference temperature are checked to see if they are the same. A recursive calculation controls the delta temperature value and selects the reference white point to give an exact color temperature correction. If the color temperature is the same (within the delta), processing is not done. If the color temperature is different, the frame is changed to the desired color temperature.

A ratio method is used to modify the color temperature. The CIE temperature to incoming frame temperature ratio is then applied to individual RGB data of the input frame to set the desired color temperature. At this point, correlated color temperature conversion is then achieved.

Figure 4: CTC IP Block Diagram

Table 4 defines the signals in the CTC module.

Table 4: Signal Descriptions of the CTC Module

The value of the input color temperature register indicates a standard temperature value (6500K, 8000K, or 9300K) as the target color temperature. The values are selected by an external DIP switch. Then CIE standard white point values are determined. These respective RGB white point values are used for further operation. By default, color temperature is not changed; it will bypass the input data. After selecting the color temperature at the start of the next frame, reference white point values are updated in the color correction module.

Frame White Point Estimation

To estimate the white point, the following algorithm is used. First, the pixel with the maximum sum of RGB over the entire frame is located. Related RGB values that represent this sum are considered as white points for that particular frame. Then this white point is updated at the start of the next incoming frame.

Color Temperature Correction Modules

In the CTC module, the incoming RGB values of the entire frame are corrected to the new temperature. For correction of these values, the ratio multiplication method of correction is implemented. For example, for the R-value of a pixel the correction in Equation 1 is used.

Equation 1

Where:
• Rin = Present R value of input pixel
• Rwt = CIE white point value for a standard temperature
• Rwf = R value white point of the previous frame
• Rout = R value of CTC corrected output pixel
The ratio remains constant over the entire frame interval. The same procedure is
also applied to the G and B values. At every clock cycle, pixels are simultaneously manipulated.

The ratio Rwt/Rwf remains constant over the entire frame interval. The same procedure is also applied to the G and B values. At every clock cycle, pixels are simultaneously manipulated.

The CTC_PGC_DATA_RDY flag is enabled when the color temperature correction module is ready to send data to the next module, the precise gamma correction block.

DIP Switch Settings

Table 5 shows the DIP switch settings for color temperature correction.

Table 5: DIP Switch Settings for the CTC Module

Device Utilization for the CTC Module

Table 6 summarizes the resources used in the CTC module. Device utilization is based on the Spartan-3E XC3S1600E FG484 FPGA on the Display Development Board.

Table 6: Resource Utilization for the CTC Module

Precise Gamma Correction

Introduction to Gamma

A gamma characteristic is an exponential relationship that approximates the relationship between the encoded luminance in a display system and the desired image brightness. Mathematically, a generic function is: Output = Input Function ^ (Gamma), or the inverse function to precorrect the data before it is displayed. Many displays show a nonlinear relationship between input and brightness output; hence, the need for gamma correction.

Uncorrected images or the incorrect gamma can cause poor contrast, poor color balance, and an improper overall light level. In addition, it is difficult to correct these image deficiencies with other color adjustments. Therefore, it is important to first encode the proper gamma for all images.

For example, in the case in Figure 5, the linear encoded (uncorrected) input signal Vs shows a large jump in perceived brightness from 0.1 to 0.4 and a much smaller increase from 8 to 10. Basically, the gamma function is applied to the input to achieve a linear output intensity for each input step for this display, as is desired with output I. Correction can also be applied to enhance perceived image quality.

Figure 5: Uncorrected (Vs) and a Gamma-Corrected Intensity (I)

Gamma Correction Implementation

A gamma curve of a 10-bit width was chosen to increase the accuracy of the output because the 10-bit output can be approximated to the nearest integer with more degrees of freedom. The 8-bit and 10-bit gamma curves are shown in Figure 6 and Figure 7, respectively, for comparison. The curves show the gamma-corrected luminance value with respect to the pixel input. The gray curve has the 8- or 10-bit resolution and the black curve is the desired response.

Figure 6: 8-bit Gamma Curve versus a Desired Linear Response

Figure 7: 10-bit Gamma Curve versus a Desired Linear Response

The figures clearly show that the 8-bit output produces a step-like function and the 10-bit output produces the desired smoothness and fit to the output.

Equation 2 is used for 10-bit gamma correction.

Equation 2

Where:
• X = an RGB input (integer representation an individual 8-bit R, G, or B value)
• Y = the 10-bit gamma corrected R', G', B' output
• Gamma = the gamma factor (programmable)

Round (Y) takes the nearest integer if the value of the decimal value is greater than 0.5; otherwise, it truncates the decimal part. The output is in a 10-bit format.

Detailed Datapath Description

External DIP switches are set to the value of gamma to be applied to the input data. The gamma functions are applied individually to each R, G, B color through a series of look-up tables (LUTs). The output data is in the form of 3x10-bit data for R'G'B'.

When precise gamma correction is complete, data-ready flags are enabled for the next module: the image dithering engine. It is also possible to bypass this block via an external DIP switch.

Figure 8: Block Diagram of Precise Gamma Correction

Table 7 defines the signals in the PGC module.

Table 7: Signal Descriptions of the PGC Module

Table 7: Signal Descriptions of the PGC Module (Continued)

The reset state of all flip-flops, boundary signals, and registers is logic 0" for all bits.

DIP Switch Settings

Table 8 shows the DIP switch settings for precise gamma correction.

Table 8 shows the DIP switch settings for precise gamma correction.

Device Utilization for the Precise Gamma Correction Module

Table 9 summarizes the resources used in the PGC module.

Table 9: Resources for the PGC Module

Image Dithering Engine (IDE)

Introduction to Dithering

Dithering is a technique used to create the illusion of color depth in displays with limited color depth. In a dithered image, colors that are not available are approximated by a mix of colored pixels from within the colors that are available. The human eye perceives the mixture as a different color.

For example, a display with only black or white colors can be used to create an image with gray colors by use of dithering (see Figure 9). The interlaced black and white pixels create the illusion of gray.

Figure 9: Creating New Colors by Use of Dithering

Some display devices have color depth less than the color depth of the input data (for example, eight-bit input data and six-bit display color depth). The input data is either truncated orrounded, but this approach usually produces both a loss of detail and may produce large, banded areas of a single color that differs significantly from the original image. Dithering is used to enhance these images.

Image Dithering Algorithm Description

The IDE module receives 30-bit (10 bits of data x3 for R'G'B') pixel streams from the PGC module.

The image dithering engine operates only on the active pixels. It uses a spatial dithering technique with a 2x2 dithering matrix for 10- to 8-bit dithering. When a 3x10 bit data stream comes in, for example, the two least significant bits (LSBs) of the three R,G,B colors contain the most "fine" color information and are selected away from the eight remaining MSB bits.

The two LSB truncated bits effectively are an "error." These two bits can have any value from 00 to 11 (binary) providing four finer color levels (0%, 25%, 50%, and 75%) to the remaining eight bits. This error is spread over adjacent pixels.

The following example shows the weights in the 2x2 matrix:

The following example shows how the above weight table is spread across the display space.

Each weight is actually a threshold value. If the last two-bit value of the input pixel is greater than the entry in the table for that position, the energy level represented by those two LSBs is added to the remaining bits, while making sure that the resultant eight-bit number does not overflow.

To eliminate a noticeable pattern, the weight table can be rotated every two lines or every frame, which adds a temporal dithering over the spatial dither.

Also, the matrix weight can be randomly rotated to provide randomness over the dithering behavior, which is good for a video screen display. When dithering with the least significant two bits of input data, the IDE uses spatial, tempo-spatial, and random spatial dithering with 2x2 pixel blocks.

When complete, the 24-bit dithered data (eight bits for each R, G, and B) are sent to the LVDS/DVI TX interface along with a dither_data_ready signal.

Figure 10: Functional Description of Image Dithering Engine (one color shown)

Table 10 defines the signals in the IDE module.

Table 10: Signal Descriptions of the IDE Module

DIP Switch Settings

The IDE module is modified by using the user push button settings (see Table 11).

Table 11: DIP Switch Settings for the IDE Module

Device Utilization for the IDE Module

Table 12 summarizes the resources used in the IDE module.

Table 12: Resources For the IDE Module (XC3S1600EFG484)

The LVDS transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock's 28 bits of input data are sampled and transmitted. Both the LVDS and DVI interfaces are provided simultaneously on the Spartan-3E Display Development Board.

The RGB Output interface consists of 24-bit RGB data and four bits of timing and control signals (Clock, HSYNC, VSYNC, Data Enable).

LVDS Transmitter Functional Block Diagram

The LVDS TX module (see Figure 11) consists of a DCM and a serdes_4b_7to1 module. The DCM generates the clkx3p5 and clkx3p5not clocks, which are each 3.5 multiples of the input clock. These two clocks are used inside the serdes_4b_7to1 module for 7-to-1 serialization of the 28-bit data in four lines.

This module does the serialization of the 28 data lines into four channels by multiplexing, using the clkx3p5 and clkx3p5not clocks.

Figure 11: Block Diagram of LVDS Transmitter

Table 13 shows the data bit encoding for the LVDS channels (the data is transmitted LSBs first).

Table 13: Data Bit Encoding on the LVDS Channels

Top-Level Design Hierarchy

The design files are used in the following hierarchy, including testbenches. The design files are located on the Xilinx website at http://www.xilinx.com/bvdocs/appnotes/xapp928.zip.

Figure 12: Module Hierarchy

Device Utilization for Top-Level Entity

Table 14 provides the synthesis results for the entire system.

Table 14: Complete System Synthesis Results

System-Level I/O Signals

Figure 13 shows an I/O diagram of the display panel solution in a Spartan-3E FPGA.

Figure 13: I/O Diagram of Display Panel Solution in FPGA

The following signal types are taken from the CORE specifications:
• I: Input is a standard input-only signal
• O: Output is standard output

The following signal naming conventions apply:
• All active-Low signals have a suffix of "_N"
• The suffix '+' denotes the positive line of a differential signal
• The suffix '-' denotes the negative line of a differential signal
Table 15 summarizes the signals for the Spartan-3E Display Development Board.

Table 15: Display Development Board Signal Descriptions

Figure 14 shows sync timing relations among VSYNC, HSYNC, and DE signals. (Note: the Sync polarities can change depending on the target panel resolution.)

Figure 14: Signal Relations in Reference Design

Conclusion

These design files present a series of video processing algorithms on a Xilinx powered development board to quickly start a display development program. Any of the IP blocks can be customized to your needs on any target Xilinx device. In addition, new video processing blocks can be added to this system to quickly validate your display video enhancement algorithms.

January 3, 2008

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