Mobile product system architects and designers face an increasingly difficult challenge. Products themselves are becoming more complex, while the schedule and budget for product development are shrinking. The key to meeting these design challenges is to build new products from a common platform that is flexible enough for customization and enhancement. The customer specific standard product (CSSP) approach that QuickLogic has pioneered provides such platforms.

Consumers are insatiable in their demands for more features and greater sophistication in their mobile products. They also require long battery lifetimes, low product costs and, above all, novelty. This leaves development teams with a demanding task: they need to create complex products that provide both the common features consumers expect as well as unique features that differentiate the product from its competitors.

These feature sets change rapidly. The mobile consumer market is evolving so quickly that the window of opportunity for a new product is often less than a year before the next product generation renders it obsolete. New product features are also evolving, and proliferating, rapidly. A new product feature that becomes popular in the market effectively forces all subsequent product designs to incorporate that feature to remain competitive. To meet the demand for novelty, design teams must get products to market quickly and often.

Regional variations in the mobile market amplify the challenge. Product design specifics often must vary by region. These variations arise from regulatory and technological differences among regions as well as from differing consumer preferences. Cell phones for the US market, for instance, differ from cell phones for the Asian market both in the signaling format and the feature sets that customers expect. Thus, design teams must produce regional variations for their products as quickly and as often as the products themselves.

Along with meeting the need for rapid creation of differentiated products, design teams must work within the constraints of a price-competitive market. Consumers expect that, over time, products with the same features and functions will have lower prices and products that have more features and functions will come in at the same price point as the previous generation. Development team design decisions must therefore result in reduced bills of material and support the streamlined supply chain management needs for cost-effective manufacturing. Further, design teams must operate under tight development budget constraints. Failure to address these market realities results in costs that destroy product profitability.

Traditional design methods cannot meet all these design constraints simultaneously. A design built upon standard, discrete logic components cannot achieve the required price points or small size that mobile devices require. While processors may form part of a design, products that are based on processors alone will not have the needed performance; there are too many functions that need to operate concurrently. The successful design of mobile products requires the use of components that offer highly-integrated standard functions in hard-wired logic while offering the flexibility of adding custom functions for product differentiation.

Traditional Design Approaches Fail

In the past, design teams used one of two approaches to combine integration with design flexibility: full-custom chip design or semi-custom chip design. Creating a full-custom chip, also called an application-specific integrated circuit (ASIC), is an expensive proposition. It requires design teams to have considerable chip design experience, either in house or hired, and typically takes 18 months or longer to complete. ASIC design also has a substantial non-recurring engineering (NRE) expense. In addition to cost of the design effort, developers must pay millions of dollars to create the mask sets needed for manufacturing.

There are also production challenges associated with the use of ASIC designs. To keep component costs low, production volumes must be substantial. This results in a high inventory cost for the design along with substantial risk. The market’s rapid evolution may result in an ASIC design becoming obsolete before inventory is depleted, resulting in the loss of any work-in-progress (WIP) investment.

The semi-custom chip approach is often called Structured ASIC. Structured ASIC vendors seek to reduce the NRE costs of the ASIC approach by starting with a chip that is fully designed up to the metal layers. Development teams can then simply hook up the functions within the chip to create their unique design. This approach limits mask costs to the last few fabrication layers and shortens fabrication time.

A third approach is application-specific standard products (ASSPs). ASSPs are dedicated chips for a specific application segment or market. Unlike ASICs or Structured ASICs, ASSPs are designed with standard functionality that can be sold to multiple customers. While the ASSP reduces design complexity, along with the costs, they are limited to utilizing the pre-designed functions, leaving little opportunity for product differentiation at the chip level. Instead, differentiation must come from software. ASSP designs are also hardpressed to keep pace with rapid market changes, effectively reducing the time-in-market for end platforms and products. Developers must wait for the ASSP vendors to complete a new chip-level design in order to offer new features using the ASSP approach.

The three traditional approaches to creating components with high integration and design flexibility thus fall short of meeting today’s design needs. QuickLogic has pioneered a new, fourth approach that can meet the challenge: the customer specific standard product, or CSSP. This approach combines the high integration and performance of hard-logic design with the flexibility needed for customization. It also addresses the low-power needs of mobile devices, reduces development effort, speeds time-to-market for initial products, improves timein- market by supporting product variations, and virtually eliminates WIP exposure.

The CSSP Design Approach

An illustration of the CSSP approach appears in Figure 1. The base chip, called a CSSP platform, is a standard, fully fabricated component. It contains a number of functions implemented in hard-logic cores that capture a mobile device design’s common requirements. These cores have tested and proven functionality and offer the high performance andsmall silicon footprint expected in a highly-integrated design, but with a difference. The cores are configurable, able to assume different “personalities,” so that a single core can address one of many different requirements.

Figure 1: The CSSP platform provides a combination of configurable hard-logic blocks and a programmable fabric toblend hard-wired performance with design flexibility.

The storage core in the upper right typifies these configurable cores. Depending on the product development team’s needs, this core can serve as an SD or MMC memory card controller, a managed-NAND Flash memory controller, or control a hard disk drive as a CE-ATA host. This gives development teams a range of choices for their design’s storage interface, allowing the creation of many design variations from the same hardware.

Along with the hard-logic cores, the CSSP offers a programmable fabric. Based on QuickLogic’s patented ViaLink™ technology (see Figure 2), this fabric provides a highly compact, low-power resource that can implement virtually any logic function the development team requires. The fabric is non-volatile, so once programmed it does not need any external memory-based boot source nor does it suffer any start-up delay. Simply speaking, it functions just as hard-wired logic would.

Figure 2: Patented ViaLink technology provides the basis for programmable fabric that yields compact, non-volatile circuitry with low-power demands.

The programmable fabric gives the CSSP a degree of flexibility unmatched in ASSPs. QuickLogic supports the CSSP fabric with an extensive library of functional cores, including processor interfaces, from which development teams can choose for implementing their unique design requirements. These tested and proven cores are optimized for the programmable fabric, providing high performance while requiring a minimum of resources. These library resources help ensure that custom designs can be implemented in a CSSP with minimal design time and effort.

QuickLogic’s CSSP solutions are market-specific design platforms, each targeting a specific mobile device market. The platforms implement, in hard-logic cores, the baseline features and standard variations the mobile device needs to offer. The programmable fabric provides additional resources for adding product differentiation features as well as implementing new standard features that the market comes to demand. As a result, a CSSP platform can serve as the hardware basis for a unique device design, regional variations on that design, and subsequent generations of the design that incorporate additional features.

Designing with CSSPs

The design process for utilizing a CSSP aims at speeding the mobile device’s time-to-market while minimizing the development team’s design effort and risk. QuickLogic CSSP architects work with the customer’s development team to define the specifications for their unique CSSP device. Then, QuickLogic’s internal System Solution Team (SST) chooses one of the available CSSP platforms available as stock components in the PolarPro™ or ArcticLink™ families and implements a design to meet the specifications. QuickLogic delivers packaged and tested CSSP components, fully programmed with the customer’s custom design, in whatever volumes are required.

The CSSP approach offers significant advantages to the mobile device design team. The approach provides proven functionality, yet is highly customizable, to provide product differentiation and variation. The compact nature of ViaLink technology, along with the hard-logic cores, ensures that the final design occupies a minimal footprint, keeping both component and board costs low. ViaLink also ensures that the design has a low power demand, supporting long battery life, because ViaLink does not require the use of active circuits to maintain the logic implemented in the programmable fabric.

A CSSP-based design represents low risk to the development team. Design times are short and do not require the customer to have in-house expertise. QuickLogic’s SSTs handle the detailed design steps. Inventory risks are minimal because fabricating the customized CSSP requires only electrical programming of a stock wafer,final test, and packaging. This allows QuickLogic to support buffer stock and respond to demand by drawing from a die bank rather than starting the production of new wafers. Customers only order as many finished devices as they currently need yet are ensured that upside demands can be quickly met.

CSSP Platform Families

QuickLogic currently offers two CSSP platforms: the PolarPro family and the ArcticLink family. Both offer combinations of hard-logic cores and a programmable fabric designed for power-sensitive mobile devices.

The PolarPro family offers designers a wide range of size, performance, and cost options. The family’s hardlogic cores include memory controllers for handling SRAM and FIFO structures as well as direct memory access (DMA) transfers. These blocks help designers enhance the capabilities provided by the application processors, adding connectivity solutions and custom functions. The family also offers a processor interface that is optimized in the programmable fabric for performance, CPU utilization, and battery life. Family members provide a wide range of capacities, from 8 to 240 Customizable Building Blocks (CBBs), and are available in small form-factor packaging or as known-good-die to address space-constrained applications. Industrial and military-grade versions of the PolarPro family are also available.

The ArcticLink family offers several different hard-logic cores. One is a Hi-Speed USB 2.0 On-The-Go controller complete with a physical layer (PHY) driver and ULPI automotive system interface. The second block is a high-speed storage interface that is configurable for use with a variety of memory cards, managed NAND, or a CE-ATA disk drive. As with the PolarPro family, the ArcticLink platform also offers a configurable processor interface optimized for performance, CPU utilization, and battery life. In addition to the hard-logic cores, ArcticLink family members offer 20 CBBs.

Along with allowing the incorporation of unique features into the CSSP, the programmable fabric blocks offer development teams an opportunity to extend the device’s standard function offering where needed. To support the rapid and efficient implementation of standard functions into the fabric, QuickLogic offers a substantial library of proven system building blocks. These blocks have been tested and proven and are optimized for performance and efficient use of the programmable fabric resources. A partial list, shown in Table 1, indicates the range of functions available and the resources they occupy.

a. When using hard-logic implementation

Table 1: QuickLogic supports its CSSP platforms with an extensive library of proven system building blocks, such as the storage functions shown here, optimized for implementation in the platform’s programmable fabric.

Full System Design Support

QuickLogic realizes that, in today’s design environment, a component by itself does not fully meet a development team’s needs. Hardware design support, software drivers, and packaging are also critical needs that vendors must address. QuickLogic provides a full range of services and libraries to address these needs as well.

On the hardware development front, QuickLogic supports customers in two ways. First, its Customer Solutions Architects (CSAs) help development teams determine the best way to utilize a CSSP platform in their design. Working closely with the development team’s designers, the CSAs help create detailed specifications for the functionality and performance of a customized CSSP.

Once the specifications are complete, QuickLogic’s System Solution Team (SST) steps in to implement the design. The SST handles the details of configuring the personality of hard-logic blocks, implementing additional standard functions in the programmable fabric, and implementing the customer’s unique functions in the fabric. Support from the SST carries through the design phase into test and system integration. SST members work along side customer development team members at the customer site to ensure that the customized CSSP functions as intended.

To aide a development team’s software development effort, QuickLogic supports its CSSPs and library logic blocks with a full range of device drivers. Drawing on its experience with WinCE, Windows Mobile, and Linux operating systems, QuickLogic has created drivers for each OS for every block. The drivers are optimized for the CSSP implementation and are fully supported during the customer’s hardware/software integration phase.

Packaging Requirements

Logic and software design command much of a development team’s attention, but packaging is also a critical design aspect. The package that a CSSP component occupies can affect the final product’s size, the amount of circuit board space used, and board costs. It can also impact decisions on what features to implement in the design when adding capability means using a larger die.

QuickLogic works with industry-leading package vendors to offer its CSSP platforms in state-of-the-art housings. This allows CSSPs to be available in bare die or in a variety of packaging sizes, including 6x6 mm, 8x8 mm, and 12x12 mm surface mount styles (see Figure 3). Working closely with packaging vendors also allows QuickLogic to customize packaging for a customer’s needs. A design implemented in one member of a CSSP family, for instance, can be ported to another member with more resources in order to add functionality, yet be packaged in the same housing as the original design. This option allows development teams to upgrade their design’s functionality without impacting the board layout or size. If the design upgrades do not require additional I/O, the new CSSP can even have the same pin-out as the original.

Figure 3: Packaging options within the CSSP families ensure that development teams can meet their design spacerequirements and offer low-impact upgrade possibilities.

This level of packaging flexibility as well as the design flexibility of the CSSP is essential for today’s mobile device designs. Development teams need solutions that offer high performance, complex functionality, and design flexibility all at low risk with quick results. Platform-based design provides such solutions, and QuickLogic’s CSSP platforms address the full range of developer needs. Customers define the requirements that their customized CSSP component must meet, and QuickLogic provides the design along with software and integration support. Mobile device designers face considerable challenges, but with QuickLogic’s CSSP approach, those challenges have been solved – Your idea, Our platform, Customized for you.

January 3, 2008

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