I/O Assignment is a Daunting Challenge

As more and more designers adopt FPGA devices with higher pin counts, the process of defining the I/O pin configuration or “pinout” has become a daunting task. The challenge is to balance the requirements from both the FPGA and PCB perspectives while designing both sides in parallel. Performing early I/O pin planning helps avoid having to iterate the pinout much later in the design cycle. Prematurely optimizing a pinout specifically for the PCB or FPGA often leads to design issues in the other domain. Pinouts defined to minimize routing concerns or layers on the PCB often lead to sub-optimal FGPA implementation. Pinouts optimized for the FPGA layout often cause PCB routing difficulties. Designers need to be able to visualize both the PCB placement and FPGA physical device pins along with the internal FGPA I/O pads and related resources to understand the ramifications of their pin assignment choices (Figure 1).

Figure 1: Displaying the Correlation between Package Pins and I/O pads

Assignment choices are typically made based on the PCB component interfaces. Critical signals and buses need to be assigned to pins on the same outside edge as the component to which they interface while maintaining “clean” routing of the signals. Especially in the case of large ball grid array packages, it can be very difficult to define the I/O pins to enable all of the PCB routing to exit cleanly. Depending on the PCB technology used, routing to the internal pins of these ball grid array (BGA) devices can be difficult or even impossible at times. Utilizing the outer pins of the device can make routing easier and wire lengths shorter. An optimal pinout can often reduce the PCB layer count or the number of PCB vias required to route all signals out from the FPGA package (Figure 2).

Figure 2: PCB Routing Challenges for Large Devices

Not only should the pinout be optimized for interconnect feasibility, but also for signal integrity concerns. Critical interfaces and differential pairs often have matched timing constraints that need to be considered throughout this parallel FPGA and PCB design process. Where possible, matched signals should be handled as a group to avoid mismatched interconnect delays.

With these new devices, designers need to be able to visualize the device interconnect of the device on the PCB, and how the connectivity translates inside the chip. Effective use of internal FGPA resources is only possible with a sensible and organized I/O interface. Assigning pins in close proximity to the CPU, DSP, and RAM resources can significantly improve the routing and performance of the design. Proper use of the device clock regions can also dramatically improve performance and reduce power consumption.

Some devices also have specific I/O requirements for clocking resources, DDRs, and onboard processors , while newer devices use complex clocking schemes involving other device resources such as regional clock buffers (BUFRs), I/O delay controllers (IODELAYCTRLs), and multi-gigabit transceivers (MGTs). Proper planning and placement of I/O related resources is required for the FPGA to function as expected.

And on top of all of these considerations, FPGAs also have I/O restrictions constraining how much output load can switch simultaneously (SSO). These restrictions are device and I/O bank specific, and can cause signal integrity problems if violated. Early analysis of the pinout configuration should be performed to ensure SSO issues are avoided downstream.

Given all of these concerns along with the large number of pins on current devices, the task of defining an I/O pinout from FPGA to PCB has become a major design challenge that can make or break a design. To date, designers have used a variety of adhoc methods to define pinout configurations with none of them being an optimal solution.

Where To Start?

Designers should begin to formulate the I/O strategy as early as possible. This task can be tough in the absence of an optimal tool for the job or a completed netlist. Waiting until the PCB netlist or default FPGA pinout is defined may be too late. Typically, the PCB designer creates PCB schematic symbols in order to begin the layout before the RTL is complete. Without insight into the device, these decisions are often made without regard for the layout internal to the FPGA. There have been many cases where FPGA designers have struggled to meet performance targets for their FGPA designs because of a fixed pinout requirement driven from the PCB. With today’s devices, the pinout has to be analyzed early from both domains.

First examine the PCB physical parameters and limitations, by answering a few questions.

It may help to draw a diagram of the proposed PCB placement, including all major components with critical interfaces and buses, to determine the desired FGPA pin assignment locations. Ensure that the components are visualized correctly in terms of the side of the board they will be mounted on. Make note of interfaces that require special attention, such as high speed buses, differential pairs, etc.

Next, examine the layout of the FPGA device to understand where the physical resources exist on the silicon.

Once the FPGA interface signals are pretty well defined for the design, signal interface groups should be created. Some designers like to use a spreadsheet containing all of the I/O signals. They can then be grouped by voltage, by clocks, by interface, by bus, etc. This is really quite valuable because it begins to formulate the groups of signals to assign in close proximity. The target I/O bank or I/O banks for the interfaces can be defined and a priority to assign to outside physical pins can also be determined for optimal PCB routing.

After examining both the FGPA and PCB domains and having defined the major interface locations, the next step is to begin the task of assigning pins to I/O banks based on all of the above criteria. This is where the work begins today. In the current flow, pin assignment is a time consuming task that can involve a lot of trial and error in order to solve all of the performance and signal integrity concerns. It is often done in the absence of graphical tools that help visualize the two domains.

Introducing the PinAhead Environment

With the latest release of the PlanAhead Design and Analysis Tool, Xilinx has introduced PinAhead Technology, which addresses both the PCB and FGPA design concerns and makes I/O pinout configuration much easier. This environment is included with PlanAhead 9.1. Opening the PinAhead environment displays a set of views applicable to the task of exploring and assigning I/O port signals to physical package pins or I/O pads on the die (Figure 3).

Figure 3: The PinAhead Environment

PinAhead leverages the easy to use graphical environment of PlanAhead to display the silicon I/O pads and related resources in the Device view, and the physical device pins in the Package view.

The Package Pins view lists device package specifications according to the device data sheets. This reduces the need to cross reference the device data sheet during pinout configuration. The Package Pins view table is categorized by I/O banks allowing easy cross selection and highlighting of I/O banks in both the Device and Package views. This clearly shows the relationship of the physical pin location and the I/O pad location on the die, which simplifies optimal I/O bank selection. Pin information for each pin in the I/O bank is also displayed in the Package Pins view. The information can also be exported to a comma separated value (CSV) format spreadsheet for use as a starting point for pinout configuration.

The I/O Ports view displays all of the I/O port signals currently defined in the design. All busses are grouped and displayed in bus folders. Differential pair signals and busses are also grouped. The I/O Ports view can be populated by importing a synthesized EDIF netlist or CSV format spreadsheet with the I/O ports defined or by using the Create I/O ports command.

Both of the Package Pin and I/O Port table views can be easily sorted in a variety of ways. These list views can be toggled to display a category based list or a flat list which makes sorting and selecting extremely flexible.

Creating Empty Project to Begin Pin Planning

PlanAhead supports creating a project in the absense of a netlist for early pin planning purposes. Designers won’t have to wait until their RTL and PCB schematic is underway before thoughtfully and visually planning the I/O pinout configuration. Empty Projects also enable the Xilinx devices to be visually explored to understand their I/O resource locations and requirements. The Create New Project dialog has been extended to allow empty Project creation (Figure 4).

Figure 4: Creating Empty Project for Pin Planning

Creating and Configuring I/O Ports

PlanAhead supports importing a CSV format file with an I/O ports list to begin pin planning using PinAhead.

I/O ports can also be created and configured from scratch very quickly using the PinAhead interface. The Create and Configure I/O ports dialog boxes are displayed below (Figure 5).

figure 5a	figure 5b
Figure5: Creating and Configuring I/O ports

Prohibiting I/O Pins and I/O Banks

PinAhead provides an interface to selectively prohibit I/O pins, groups of I/O pins or I/O banks from having I/O ports assigned to them. Pins may be selected and prohibited in the Package Pins, Device or Package views. As an example, designers can easily sort the Package Pins view and prohibit all of the VREF pins.

Creating I/O Interfaces

PinAhead enables users to group related I/O ports and busses into an “Interface”. This grouping simplifies I/O port management and assignment tasks by enabling related I/O ports to be handled as a single entity. It makes it much easier to visualize and manage all of the signals associated with a particular logic interface. Interfaces can be easily copied from design to design or used to generate interface specific PCB schematic symbols.

The Interfaces appear as expandable folders in the I/O Ports view (Figure 6). Additional I/O ports can be added to the Interface by selecting them in the I/O Ports view and dragging them into the Interface folder.

Figure 6: Grouping Related Pins into Interfaces

Placing I/O Ports

As the I/O ports are created, they can be assigned to Package pins or I/O pads. Designers may wish to examine their initial PCB interconnect sketch or consult with the PCB designer to understand the desired locations and considerations for placing the various I/O port interfaces. Proper bus order and edge proximity can aid PCB routing significantly.

Individual pins, busses and/or Interfaces can be assigned to I/O pins by dragging them into either the Device or Package views. The entire group of pins will be assigned to the selected I/O pins using various assignment pattern modes. The available modes include Place I/O Ports in an I/O Bank, Place I/O Ports in Area, and Place I/O Ports Sequentially. Each mode offers a different assignment pattern for the I/O ports to be assigned to pins. Information about the number of ports being placed is provided on the cursor tool tip. The mode remains active until all of the selected I/O ports are placed.

PlanAhead attempts to maintain correct-by-assignment assignment rule. Differential pair ports will be assigned into proper pin pairs. However, pins can be manually assigned that conflict with some device I/O banking rules. The batch PlanAhead I/O related DRCs have been improved to flag such I/O issues.

Placing I/O Ports in I/O Banks

This mode enables the placing of selected I/O ports into selected I/O banks. To place I/O ports into I/O banks, select I/O ports, buses or Interfaces, and click the Place I/O Ports in an I/O Bank button in either the Package or Device view. The group of I/O ports is attached to the cursor when it is dragged over a package pin or I/O pad. A tool tip displays how many pins can be placed in the selected I/O bank. Click on a pin or pad to assign the selected I/O ports (Figure 7).

Figure 7: Placing I/O Ports in I/O Banks in the Package view

If more I/O ports are selected than will fit in the I/O Bank, the command will place the remaining I/O ports to the next selected I/O Bank, and so on until all of the I/O ports are placed.

Ports are assigned in the order that they appear in the I/O ports view. The assignment order can be adjusted by applying sorting techniques in the I/O ports view prior to assignment. The assignment order is also driven from the initial Pin that is selected for I/O Bank assignment.

PCB routing concerns for busses are taken into consideration. Pin ordering during assignment attempts to keep the bus bits vectored within the assignment area to address bus order and routing concerns.

Placing I/O Ports in an Area

This mode enables the placement of selected I/O ports into a rectangular area in either the Package or Device views. To place I/O ports into an area, select I/O ports, busses or Interfaces, and click the Place I/O Ports in an Area button in either the Package or Device view. The cursor turns into a cross symbol which indicates that you can define a rectangle for port placement. Draw a rectangle in either the Package or Device view to define the assignment area

Figure 8: Placing I/O Ports in an Area on the Device view

Placing I/O Ports Sequentially

PinAhead provides ultimate flexibility by allowing you to sequentially select package pins or I/O pads to assign the each I/O port. To place I/O ports sequentially, select I/O ports, busses or Interfaces, and click the Place I/O Ports Sequentially button in either the Package or Device view. The first I/O port in the group is attached to the cursor when the cursor is moved over a package pin or I/O pad. A tool tip displays the I/O port and package pin names. Click on a pin or pad to assign an I/O port. If more I/O ports are selected, the command is continued until all of the pins are placed.

Automatically Placing I/O Ports

PinAhead has the capability to automatically place all or any selected I/O ports to package pins. The Autoplace command will obey all I/O standard and differential pair rules, and will place Global Clock pins appropriately. The command will also attempt to group the Interfaces as much as possible.

Prohibits can be placed on individual I/O pins or I/O banks to prevent I/O assignment to them.

I/O ports can be pre-selected for auto-placement (Figure 9). To automatically place all unplaced I/O ports, select the Autoplace I/O Ports command to invoke the Autoplace I/O ports wizard (Figure 9). You can elect to place all unplaced I/O ports or allow the tool to clear them all and start over (Figure 10).

Figure 9: Autoplacing Selected I/O Ports

Figure 10: Placing All Unplaced I/O Ports

Locking Down Clock Logic

PinAhead enables the placement of other I/O related logic, such as BUFG, BUFR, I/O DELAY, IDELAYCTRL, and DCM. Clock Regions and clock related logic objects are all displayed graphically in the Device view making I/O assignment based on clocks much easier and intuitive.

These objects and placement sites are easily located in PlanAhead using the Find command. Logic connectivity can be selectively expanded and explored in the Schematic view (Figure 11).

Figure 11: Exploring I/O Connectivity using the Schematic

Logic can easily be selectively expanded in the Schematic. The logic expansion and traversal options are quite extensive allowing effective exploration of the design logic.

Locking placement of specific I/O related logic is made easy in PlanAhead. You can easily select the logic in any view and drag it onto sites in the Device view to lock them in place (Figure 12).

Figure 12: Locking Clock Logic

PlanAhead will only allow logic to be placed on appropriate sites. A dynamic cursor identifies the proper site locations as the logic object is being dragged.

PinAhead also provides the capability to selectively clear I/O pin and I/O related logic assignments by object type. Clock pins and clocking logic are defined once and are left alone for experimenting with the other I/O port assignments (Figure 13).

Figure 13: Selectively Clearing I/O ports and Clock Logic

Running I/O Port DRCs

PlanAhead includes a vast set of DRC rules to ensure a design is error free prior to implementation. These rules include many I/O and clock related rules to ensure the I/O placement is legal. Rules can be selected using the PlanAhead DRC dialog (Figure 14).

Figure 14: I/O Related DRC Rules

If violations are found, a DRC results table is displayed in which the offending logic objects can be easily located and selected.

Running WASSO Analysis

PlanAhead also includes Weighted Average Simultaneous Switching Output (WASSO) analysis to help identify potential signal integrity issues with the pinout configurations. Designers can input parasitic characteristics of their PCB. PlanAhead will analyze the various I/O banks and their neighbors and report back the utilization and status of each I/O bank (Figure 15).

Figure 15: Examining WASSO Analysis Results

Exporting an I/O Port List

The I/O port list and Package Pin information can be exported from PlanAhead in a CSV format file. The file includes information about all of the package pins in the device, as well as, design-specific I/O port assignments and their configuration.

The package pin section of the list makes a great starting point for defining I/O port definitions in the spreadsheet.

The spreadsheet can also be used to automatically generate the PCB schematic symbols required to begin the PCB layout. Often times these symbols are too large for the schematic and have to be broken up into several symbols. This can be done quite effectively using the Interface groups created in PinAhead (Figure 16).

Figure 16: Exporting the I/O ports Spreadsheet

Providing this I/O pinout configuration to the PCB designer in the form of a schematic symbol gets them on their way toward effective PCB layout. If pins do need to be swapped during layout, the changes can bee isolated within I/O banks, and should not affect the FPGA layout dramatically.

Summary

With new PinAhead Technology, PlanAhead provides designers with unique design visibility and robust capabilities to explore I/O assignment options. The environment provides device information and many unique views into the design. I/O pin planning can be performed very early in the design cycle prior to FPGA or PCB netlist generation. Related I/O ports can be grouped together into Interfaces to aid with placement and management of I/O ports. Designers can focus on assigning critical I/O ports using a variety of semi-automated placement modes. They can rely on the Autoplace command to place the remaining I/Os in legal sites. I/O related DRC rules and WASSO analysis are provided to help uncover design issues early. The I/O port configuration and package data can be exported in a spreadsheet format.

Utilizing these capabilities to thoughtfully define an I/O configuration that satisfies both the PCB and FPGA domains can lead to increased design performance and a potentially less costly PCB.

by Brian Jackson, Xilinx

March 22, 2007

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