Traditionally FPGA designers have been concerned with timing and area efficiency however as FPGAs have moved more and more into a role of replacing ASSPs and ASICs they have been pressured to develop lower power designs, produce better power estimates earlier in the design flow, and manage and sequence a variety of core and I/O voltages that often accompany FPGA implementations. Management of power has become an important consideration for FPGA designers especially those that target portable, battery-powered products. Using power-aware design techniques can help reduce consumption, increase the reliability, and lower cost of production with leaner power supplies and fewer cooling requirements.

Here are some key problems you might face with any FPGA power implementation: What will be the system-level power supply requirements? What will be the current draw? What voltage levels will be required and what power-up/down issues are there? What will be the thermal conditions of the device and will it work reliably given the environment and design I expect to run? Will I need to design in cooling mechanics to the board to counteract a hot part?

Power Theory

Power in electronic devices is often defined as the amount of work done by an electric current. Devices tend to convert work into heat, which unfortunately is not considered very useful in most applications unless your design is a heater or a light bulb! Understanding FPGA thermodynamics will help you identify the high-impact, low-effort methods to reduce power. Total power is a function of certain types of sub-power producers along with the characteristics of the process node and device packaging.

The AC portion of the power consumption, associated with used resources, is the dynamic part of the power consumption. AC power dissipation is directly proportional to the frequency and activity at which the resource is running and the number of resource units used. From equation below it becomes more obvious how power consumption can be influenced by lowering supply voltage (the largest factor), switched capacitance, switching activity of nodes, or frequency of signal transitions

CMOS FPGAs contribute to power dissipation from two primary sources: static and dynamic . Power is expressed as Joules/Second or Watts given the equations:

Where:

P = Power (Joules/Sec or Watts)
V = Voltage (Joules/Coulomb or Volts)
I = Current (Coulombs/Sec or Amperes)
R = Resistance (Ohms)
ß = Switching activity per node
C = Switched capacitance
V²_DD = Supply voltage
F = Frequency (switching events per second)

The relative contribution of PStatic versus PDynamic varies by process node. Static consumption represents a fraction of the total power dissipation in 130 nm and 90 nm device. For example, given a sample design with internal logic running at 50 MHz and I/O at 250 MHz, PStatic is around 10% in 130 nm FPGAs like LatticeECP or LatticeXP families and 20% in 90 nm LatticeECP2 or LatticeXP2 device even in a design. Most energy is consumed due to dynamic switching activity and by charge/discharge of load capacitances, which is largely a function of the user design. This convention changes at 65 nm process nodes and smaller.

Transistor physics changes at smaller geometries such that static leakage is much more significant. Static power is growing exponentially due to increasing transistor leakage. And the crossover point, where static power overtakes dynamic power, is 65 nm. Lattice Semiconductor and other FPGA suppliers address these issues largely in their respective fabrication processes and with the transistor mix used with each device.

AC power dissipation is directly proportional to the frequency and activity at which the resource is running and the number of resource units used. The P Dynamic equation above illustrates how power consumption is influenced by supply voltage (the largest factor), switched capacitance, switching activity of nodes, and frequency of signal transitions.

As FPGA technology process geometry shrinks, designers naturally benefit from reduced power consumption of smaller transistors and IC dies. However this benefit is usually offset to some degree by increased clock speeds and larger designs. The relative contribution by FPGA architectural element also changes between process nodes. As an example, the figures below illustrate contribution by resource, routing, logic such as LUT and registers, embedded block ram (EBR), etc. with the 130 nm LatticeECP versus the 90 nm LatticeECP2/M FPGA given a design that models 90% logic utilization, 100% utilization of embedded ASIC blocks such as PLL/DLL, memory, and DSP features, and 80% utilization of I/Os using a mixture of LVCMOS 1.2V and LVDS 2.5V DDR type signal standards.

Figure 1. P(Dynamic) Contribution by Resource Type (LFECP15E)

Figure 2. P(Dynamic) Contribution by Resource Type (LFE2-20E)

While overall power consumption may drop in a 90 nm device, the relative amount represented by I/Os increases significantly. This will influence what your power reduction strategy will be for a particular device family.

Thermal Management

Heat, the byproduct of work performed by an IC, must be addressed with techniques to ensure an FPGA will operate within the junction temperature specification. Semiconductor devices will operate normally as long as the temperature does not exceed an upper limit specified as the ambient temperature and the temperature of the silicon junctions. When this upper limit is exceeded, the IC stops operating normally and will be damaged. Thermal management is indispensable when using the IC for high power application or using it under a high operating temperature.

To avoid reliability issues, semiconductor vendors specify a maximum allowable junction temperature in device data sheets. The designer should always complete a thermal analysis of their specific design to ensure that the device and package does not exceed the junction temperature requirements. The internal data shown is relative and actual values depend on a variety of factors such as: die size, paddle size, airflow, power applied, PCB design and the user application itself.

Although total power, ambient temperature, thermal resistance and airflow all contribute to device thermodynamics, the junction temperature (Tj), as specified in the device data sheet, is the key to device operation. For example, the allowed junction temperature range for the LatticeECP2/M with a variety of architectural blocks including DSP, memory, and SERDES I/O, is 0°C to 85°C for commercial devices and -40°C to 100°C for industrial devices. AC characteristics are guaranteed when the device is operated in these ranges. The reliability limit of junction temperature for this generation of device technology is 125°C. You should also be aware of the Min/Max numbers for supply voltages since they may help you reduce static power.

Operating a device at a higher temperature also means a higher static current (SICC). The difference between the SICC and the total ICC (both Static ICC and Dynamic ICC) at a given temperature provides the dynamic budget available. If the device runs at a dynamic ICC higher than this budget, the total ICC is also higher. This causes the die temperature to rise above the specified operating conditions. Reducing one or more factors: power, ambient temperature, thermal resistance or airflow, can be varied and controlled to reduce the junction temperature of the device.

The concept of thermal resistance is used when considering heat dissipation. In an IC, thermal resistance (θ) indicates the steady state temperature rise of the die junction above a given reference for each watt of power (heat) dissipated at the die surface. Its units are °C/W. The most common examples are θ_JC, Thermal Resistance Junction-to-Ambient (in°C/W) and θ_JC, Thermal Resistance Junction-to-Case (also in °C/W). Another factor is θ_JB, Thermal Resistance Junction-to-Board (in °C/W).

In addition to the device and package, the thermal characteristics of a circuit depend on the operating temperature, device power consumption, and the ability of the system to dissipate heat. The maximum junction temperature of a device can be calculated as shown:

Where T_J, T_A, T_C, and T_B are the Junction, Ambient, Case (or Package) and Board temperatures (in °C) respectively. P is the total power dissipation of the device. θ_JA is commonly used with natural and forced convection air-cooled systems. θ_JC is useful when the package has a high conductivity case mounted directly to a PCB or heat sink. θ_JB applies when the board temperature adjacent to the package is known.

For the power (P=Vcc * Icc) factor I_CC may be estimated from the power consumption section of individual device data sheets or as an output of power estimation software. The chart below illustrates thermal resistance (θ_JAand θ_JC) characteristics across the package range of the LatticeECP2/M family. It demonstrates the benefits of certain package types and airflow versus a still air environment.

Figure 3. Thermal Resistance LatticeECP2/M Packages

When designing a system, designers must make sure devices will operate at specified temperatures within the system environment. This is particularly important to consider before a system is designed. With FPGA power estimation tools, you can predict device thermodynamics and estimate the dynamic power budget. The ability to estimate a device’s operating temperature prior to board design also allows the designer to better plan for power budgeting and airflow.

Managing Power Consumption

Given a target application where the designer must account for power consumption a power-closure methodology should be adopted. In the first step the designer should look for opportunities to create power-friendly RTL. High-impact, low-effort practices include targeting embedded blocks, gray encoding of smaller FSMs, and organizing blocks in a manner that area optimization will not overly impact performance. If the FPGA is a higher-density, 90 nm device, I/O programming and switching should be given extra scrutiny to save power. Next power-friendly synthesis and place and route optimizations such as register retiming, and area optimization should be applied. Finally a robust test bench that reflects actual operating conditions will help to build an accurate activity-factor and toggle-rate factors for post-simulation analysis in with the power estimation software.

Figure 4. Power Closure Methodology

There are several design techniques that can help reduce overall system power consumption.

Static power reduction methods include:

• Use sleep mode if available.
For example, during a period of system inactivity the LatticeXP "C" (VCC= 1.8/2.5/3.3V) devices can be placed in sleep mode. During sleep mode the standby current is reduced by over 1000X. Power supplies do not have to be switched, they are in their operating range.

• Reduce operating voltage.
Use VCC & VCCJ at the lower end of the device specification.

• Minimize the operating temperature, by the following methods:
- Use packages with lower thermal impedance that can dissipate heat better.
- Place heat sinks and thermal planes around the device on the PCB.
- Use airflow techniques such as mechanical guides and fans.

• Reduce switched capacitance and frequency of I/Os.

• Decouple I/Os when in sleep mode.
If this isn’t possible, power down the core and leave the VCCO applied.

• Reduce I/O voltage swing.
Keep I/O drive as low as possible, for example if driving 3.3V CMOS, try using 2.5V-3.0V VCCO. This can degrade noise immunity, but can help power. Use lower voltage standards with I/Os.

• Use slew rate controls to reduce output-switching current.
Some FPGAs provide control over LVCMOS or LVTTL output buffer that can be configured for either low noise or high-speed performance.

Dynamic (AC) reduction methods include:

• Enable synthesis area optimization.
Reduce the span of the design across the device. A more closely placed design utilizes fewer routing resources for less power consumption.

• Target embedded ASIC blocks.
EBR, DSP, PCS blocks of modern FPGAs will have lower consumption over generic LUT/register logic.

• Use signal-encoding optimization of counter/FSM modules.
For example, a 16-bit binary counter has, on average, only 12% activity factor and a 7-bit binary counter has an average of 28% activity factor. On the other hand, a 7-bit Linear Feedback Shift Register (LFSR) can toggle as much as 50% activity factor, which causes higher power consumption. A Gray code counter, where only one bit changes at each clock edge, will use the least amount of power, as the activity factor is less than 10%.

• Use optimum clock frequency. Reduces power consumption, as the dynamic power is directly proportional to the frequency of operation. Designers must determine if a portion of their design can be clocked at a lower rate, which will reduce power.

• Use clock-gating optimization.
As clock signals are a major contributor to power dissipation because they switch at all times, clock gating can help reduce excessive switching in synchronous registers. Gate clocks prior to primary/secondary route resources of the FPGA.

• Time division multiplexing (TDM) type arithmetic.

• Synchronous versus asynchronous counter implementations.

FPGA Power Estimation Tools

Like simulation, FPGA thermal analysis, is a verification flow that runs parallel to traditional FPGA implementation tools. In the ispLEVER design flow for Lattice FPGAs designers can estimate power consumption at any stage: pre-synthesis, post-route, and post-simulation with the Power Calculator application. FPGA power estimation software tools typically allow designers to estimate power consumption at three different levels of accuracy:

1. Estimate-driven where utilized resources and toggle activity is manually entered.

2. Post-PAR where post place and route resources are imported for a more accurate utilization model.

3. Post-simulation where toggle activity produced by an HDL simulator is imported for a more accurate activity factor and toggle rate model.

Power Calculator uses input parameters, such as device characteristics, voltage, temperature, device variations, airflow, heat sink, resource utilization, activity, and frequency to calculate the device power consumption. The calculator reports both static (DC) and dynamic (AC) portions of the power consumption and the predicted junction temperature (TJ). Pre-synthesis, switching activity is estimated with the activity factors of logic blocks, and toggle rates of I/Os. If you use the Power Calculator after place and route, you can import the actual device utilization through native circuit description (NCD) database. Power calculation is most accurate when the system uses the post-map, post-place, or post-route NCD results. An optional value change dump (VCD) file containing activity factors and toggle rates based on simulation results will further increase accuracy.

AC power is derived by the following power equation:

Total AC Power (Resource) = KRESOURCE * fMAX * AFRESOURCE * NRESOURCE

Where:

KRESOURCE is the power constant for the resource in mW/MHz.
fMAX is the max frequency at which the resource is running. Frequency is measured in MHz.
AFRESOURCE is the activity factor for the resource group. The Activity Factor is a percentage of the switching frequency.
NRESOURCE is the number of resources used in the design,

The Activity Factor % (or AF%) is defined as the percentage of frequency (or time) that a signal is active or toggling the output. Most resources associated with a clock domain are running or toggling at some percentage of the frequency at which the clock is running. Users of the calculator can enter this parameter as a percentage manually or import the activity based on simulation results. AF can be calculated for each routing resource, output or PFU. If no simulation results are available, the general recommendation for a design occupying roughly 30% to 70% of the device is to provide an AF% between 15% and 25%. AP accuracy depends on clock frequency, stimulus to the design and the final output.

A key input parameter for I/O consumption is the I/O toggle rate. While AF% is applicable to the PFU, routing, and Memory Read Write Ports, of memory blocks, etc. The activity of I/Os is determined by the signals provided by the user (in the case of inputs) or as an output of the design (in the case of outputs). The rates at which I/Os toggle define their activity. The Toggle Rate (or TR) in MHz of the output is defined in the following equation:
Toggle Rate (MHz) = 1/2 * fMAX * AF%

Summary

One of the most critical factors in design today is reducing the system power consumption and is especially important for hand-held devices and other modern electronic products. Power reduction techniques can vary depending on the type device targeted and characteristics of the design. An understanding of the sources of FPGA power consumption, static and dynamic, core and I/O, will influence your power reduction strategy and by adopting power-aware design techniques along with estimation methodology will help you meet the operating specifications of your device.

Troy Scott has been helping design and promote EDA products for 15 years. He is a Senior Product Marketing Engineer at Lattice Semiconductor Corporation. He welcomes feedback and can be reached at troy.scott@latticesemi.com

May 31, 2007

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