Overview

Over the last decade, digital wireless technologies have become one of the leading drivers of semiconductor growth and also a source of increasing design complexity. In nearly every application category, new wireless standards are pushing for higher performance and capacity by using more sophisticated algorithms. A good example is 802.11n, the much anticipated new WLAN technology that promises to deliver data rates up to 600Mbps. Other examples include WiMAX, 3G and 4G Cellular technologies, Digital Video Broadcast (DVB), Software Defined Radio for military radios, and so on. Most of the end markets driving these applications are either in early stages of very rapid growth, or are more established markets under pressure to upgrade performance and capacity to meet competitive demands. In either case, the demands trickle down to the design teams who are challenged to deliver the increasingly complex IP in less time.

In the past, the semiconductor industry has met this type of challenge by introducing higher levels of design abstraction. The most recent example is the growth of Verilog and VHDL methodology over the last 15 years for logic design. IC engineers can rapidly model, simulate, and synthesize implementation at the logic level which realizes a huge productivity improvement over design at the gate or transistor level.

The same automation and productivity gains can be applied at the DSP and wirelesss algorithm level by providing an abstraction layer to RTL implementation. This abstraction will intrinsically be quite different, however, because DSP is dominated by digital arithmetic and specialized signal analysis techniques. A good high level abstraction layer for DSP should shield the designer from implementation details of the mathematical operations like multipliers and adders. Of more significance is automating the architectural optimization techniques that are so common for practical arithmetic datapath realization. This includes pipelining for performance, and resource sharing expensive operators like multipliers for area and multi-channel efficiency. These are very common and important optimizations, and a good DSP abstraction layer should automate them and save the designer the time and effort of implementing them by hand.
The Synplify® DSP software from Synplicity achieves this goal by giving designers a technology independent, high-level DSP modeling environment and a synthesis engine that automatically creates optimized DSP arithmetic into silicon.

With a comprehensive DSP library, excellent fixed-point analysis tools, multi-rate capability, and hardware abstraction, algorithms are easier to describe and verify. By providing constraint driven architectural synthesis, design-space exploration is enabled, achieving more optimal results and full device and technology portability. Figure 1 shows the key elements of this design flow.

Figure 1

Wireless Algorithm Requirements

The development of wireless communications presents unique requirements for algorithm design and implementation. The most prominent is the significant use of multi-rate filtering along both transmit and receive signal chain. There can be more than 2-3 rate changes each, depending on the IF processing stages as shown in Figure 2. IF processing usually operates at much higher sample rates than baseband processing, thus the speed differential in clock domains can be a significant ratio, i.e. 256X or higher.

Figure 2: Example of Wireless Algorithm Design Requirements

For implementation, this creates an optimization opportunity for area and logic optimization in the slower clock domains. Resource sharing can be used with the higher clocks to minimize expensive operations, i.e. multipliers. However, this comes at the cost of additional design effort, and also verification/simulation time.
This extra effort is compounded by another major requirement of wireless algorithm development: the more complex simulation and analysis required to verify the channel performance. Comprehensive testing of a communication channel requires many simulations to plot the statistical bit error rate (BER) and compare to a theoretical curve. Deviations from the curve indicate non-optimal performance or errors in the implementation.
Together, the verification complexity and extra RTL coding for optimal results can significantly decrease productivity and time to market. DSP synthesis methodologies can alleviate these problems and increase reliability of the design process. The table in Figure 2 summarizes how the Synplify DSP tool addresses these issues and the following sections will illustrate these benefits using QAM modulation.

Design Capture Example

Figure 3 shows an example of how baseband processing for a simple QAM modulator/demodulator (modem) can be captured and modeled using the Synplify DSP library. The transmit function flows along the top of the diagram and includes a modulator/symbol mapping function, followed by a pulse shaping filter with an upsample x4. The receive functions flow along the bottom with the reverse functionality: a matched receive filter, downsampling x4, and the symbol demapper. The transmit output is sent through the Simulink AWGN channel model into the receive input. This creates a digital loopback mode that allows for measuring the modem’s BER performance.

The Digital Modulation and Digital Demodulation blocks are setup to use QAM256, gray encoded constellations as shown in Figure 4. The demodulation is set to hard decision, although it does support soft decision for use with Viterbi decoding. The filters use square root raised cosine coefficients with a rolloff of .5.

Figure 3. QAM Modem Design

Extensible IP Methodology

The demodulator is a Synplify DSP custom block, which means it uses a Matlab/Simulink script to create a user interface and to generate the demodulation logic under the hood. This provides another big benefit to wireless development: the ability of the user to create custom library functionality that is implementable and optimizable by the DSP Synthesis optimization flow. For example, a lookup table approach is used by the default demodulator, with soft logic to support minimum distance soft decision calculations. If the designer wants to use a different method, or add further types of methods, it can easily be done by copying the block to a new library and unlocking it for editing and debugging.

Verification

Additional Simulink analysis tools can be added to this example for measuring BER performance. This includes a random data generator and bit error measurement blocks. A spectrum analyzer block can be connected to the receive input for display the spectral response of the transmitter with channel impairment. A Discrete-Time Eye-Diagram block can also connected to the receive filter output to analyze intersymbol interference ISI and verify proper matched filter operation.

Figure 4 shows example simulation results when the channel model is set to a high SNR. These analysis tools make it easy to verify proper channel waveforms and performance. In addition, the communications BER (Bit Error Rate) tool can automatically do a full calculation of the bit error rate curve of the design.

Figure 4. Example of QAM modem verification using tools from the Simulink Communications Blockset

Synthesizing an Implementation

Once a Synplify DSP model is captured and verified, it can be optimized and implemented into RTL using the Synplify DSP synthesis engine. Here is where the big benefits of a DSP Synthesis approach become obvious. From a single model or algorithm description, the designer can synthesize many implementations, optimizations, and target devices without ever changing the algorithm or verification models. This is often referred to as a “golden source” flow.
Table 1 shows an example of area optimizations that can be automatically realized for the QAM modem example above. The Folding Constraint is a user input that controls the resource sharing and the maximum clock rate. The default clock rate, without any optimization, is inherited from the sample rates specified in the model simulation. By applying higher folding factors, the synthesis tool automatically infers higher rate clocks, determines the resource sharing possible in each clock domain, and then implements the necessary logic for the resource sharing automatically. Note that this can be explored without changing the algorithm model, and without extra design effort by the user. The results show a significant reduction in multiplier use, at the expense of a small increase in LUTS and registers.

Table 1: Folding and area optimization exploration using DSP Synthesis

The simplicity of this process, the hardware abstraction of the design, and the powerful optimizations offered are the key factors that enable rapid design exploration. For example, a single “frozen” design can be targeted to a faster device with high folding factor for a small form factor in a larger design, or to a slower, lower cost device with retiming for a low-cost high performance product.

The Synplify DSP tool provides three types of optimizations:

• Retiming/pipelining for speed optimization
• Folding for area optimization
• Multi-channelization for multi-channel resource sharing

If the overall timing constraint can’t be met, retiming optimization will search the critical paths for opportunities to automatically move or insert registers to meet the overall performance goal. Obviously this is at the expense of more area and latency in the design, hence, a tradeoff of speed for area/latency. The tradeoff is controlled by the retiming parameter, which limits the amount of latency or stages inserted into the design. For example, a retiming constraint of 1 will adjust existing registers and insert new registers up to an extra latency of 1 sample clock.
Multi-channel optimization replicates the datapath in RTL, but will automatically implement resource sharing to optimize the total area, at the expense of extra clock cycles. For example, multi-channelization factor of 4 applied to the design above, will implement 4 modem “channels,” but will use a 4X clock to time share critical resources like multipliers across the different paths.

Technology and Vendor Independence

In addition to exploring optimizations from a single source model, the designer can target other devices, vendors, and technologies, making his algorithm description fully portable. This drastically improves the ROI on the effort involved in designing and verifying complicated IP like wireless communication algorithms. The synthesis engine is technology aware, that is, it takes into account the device timing characteristics for making its optimization decisions. For example, pipeline/retiming registers will be inserted differently for a Spartan3, as compared to a Virtex 4. This means better quality of results even when porting designs across vastly different IC technologies.

Benefits of Model-Based Design

The example used here is a simple design that ignores synchronization and timing recovery issues. However, it is useful for isolating and verifying key functionality, before moving on to add more complicated operation. This is a big benefit of model-based design where a designer can start small and extend his design further after verifying subsections. In this case, the next step would be to add forward error correction, automatic gain control, and symbol timing recovery. However, it is much easier to debug and verify this additional functionality when the basic modem functionality is known to be good.

Summary

Advanced wireless technologies are driving designers to design highly complex DSP algorithms into fast-growing markets. By applying advanced new DSP synthesis methodologies in the development effort, they can quickly model algorithm designs without having to write RTL from scratch. They can also quickly manipulate, optimize and retarget their designs without the need for time consuming and tedious manual coding iterations.

Chris Eddington, Senior Technical Marketing Manager, Synplicity, Inc.

September 28, 2006

[back to top]

Comments on this article? Send them to comments@fpgajournal.com