Processing power has always been on every designer's mind, but today’s market requires that designers also pay attention to power consumption. In this increasingly portable world, finding ways to extend battery life is no longer a consideration; it is a necessity. For FPGA users, power consumption can become an issue without mindful technology choices.

Designers usually do not associate low power with FPGAs because most FPGA types are SRAM and flash-based, using memory-controlled switch transistors to create the FPGA’s programmable interconnections. These memory circuit structures draw power simply to maintain the interconnect programming, giving the FPGA a relatively high power consumption even when idle. In addition, while the latest generations of semiconductor process geometry have pushed memory-based programmable logic performance to its edge the processes have also caused major problems in terms of power consumption due to increased leakage current.

Designers may not be aware, however, of an alternative programming technology, the anti-fuse, that does offer low power operation. Anti-fuses, such as QuickLogic’s ViaLink®, are an extremely fast, low power, non-volatile interconnect that eliminates the need for memory-controlled switches. The ViaLink anti-fuse element, for instance, consists of a high resistance layer (>1 GigaOhm) of amorphous silicon above a tungsten plug (ViaLink) that would otherwise bridge the insulation between two metal layers, as shown in Figure 1. When a programming voltage is applied to a selected ViaLink, the silicon permanently transforms into a low resistance material that provides a direct metal-to-metal link for the interconnect.

Figure 1 - Anti-fuse programming creates a permanent link in FPGA logic where needed, eliminating the
power demands of memory cells and interconnect switch transistors.

Typical programming resistance for a ViaLink connection is about 30 Ohms. The physical size of the programmed link is smaller than the ViaLink plug; the size of the ViaLink plug is <1/4 micron square. This small size coupled with the ViaLink material’s high dielectric constant ensures that unprogrammed links exhibit capacitive loading <1 pF. This low routing capacitance and resistance enables better circuit speed performance and lowers overall power consumption. The ViaLink anti-fuse also allows smaller die size without compromising logic density. This, in turn, allows fabrication of devices with comparable density and performance to memory-based FPGAs while using a mature semiconductor process having lower leakage current.

Power – Static, Idle, and Active

While technology choice can have a significant impact on FPGA power consumption, the power-conscious designer should also look at the device’s operating states. The FPGA will typically be operating in one of three power states: Active, Idle, or Static. Each has a different power consumption profile. Depending on the usage duty cycle the device sees in its application, any of these states may have a significant impact on a design’s average power use and long-term drain on battery resources.

The active power, also called dynamic power state occurs when the device is fully functioning, with I/Os, internal logic, and clocks toggling. As with all CMOS logic, the power demanded in the active state occurs as transistors switch, and so increases with clock frequency. Lowering clock frequency as much as possible is one step that the designer can take to lower a design’s average power.

In the static power state there is no activity on the I/Os and no clocks are toggling. The power used in this state comes from the leakage current of the transistors. Surprisingly, with shrinking process geometries, static power can surpass dynamic power as the single largest contributor to overall power consumption in an FPGA device. Here is where anti-fuse technology really pays off. It both eliminates the interconnect switch transistors and associated memory cells of memory-based technologies as well as allows use of lower-leakage semiconductor processes.

FPGA devices may also allow the designer to employ an idle power state that a device can enter when its functionality is not required for a significant period of time. For some devices this is the same condition as the static state, entered by freezing all clocks, and the dominant power use comes from leakage current. Other devices, such as QuickLogic’s PolarPro™, have a special sleep mode that can bring the idle power down even further. In the PolarPro devices, this idle power state is called the VLP (very low power) mode and is entered by activating a control pin.

True Idle Mode

The difference between a true idle mode and simply freezing the clocks to enter a static power mode lies in the handling of external signals. Even if the FPGA is not being clocked, any connection to active buses means that some of the FPGA’s internal logic is being toggled, consuming power. A true idle mode will prevent this wastage by effectively disconnecting the FPGA from external signals while idle. The VLP mode reduces PolarPro power usage from <100 uA in static mode to <10 uA in idle mode.

QuickLogic’s VLP mode works by first gating all input signal lines to prevent bus activity from toggling internal logic. To prevent the input line gating from affecting the FPGA’s internal states, special logic within the FPGA freezes the values of all registers and gates within the device before disconnecting the input signals. The circuitry also reduces internal signal levels to minimize leakage. All output lines remain at their last value to ensure that placing the FPGA into the VLP mode does not affect other devices in a design.

With proper technology selection and careful use of different power modes, power-conscious designers can now safely ignore the old high-power reputation that has plagued FPGAs. Instead, designers can employ the flexibility and performance benefits of programmable logic in even the most demanding portable applications.

by Claire Tu and Arul Chinnappan, QuickLogic®

March 30, 2006

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