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Logic Navigator Overview The ability to probe and analyze embedded signals in a design is important to rapid verification of large gate count and high performance FPGA designs. In a large design, entire logic subsystems may be essentially inaccessible from the pin IO, which limits the ability for direct verification. Proactive approaches to design debug can significantly improve the comprehensiveness and ease of analyzing complex FPGA designs. Probably the most fundamental analysis requirement for FPGAs is to allow for trace and debug of groups of embedded signals and for analysis of signals in context of either other related signals or under specific triggering events. Several FPGA venders (Xiinx, Altera, Lattice) have developed their custom debug solutions for their FPGAs. Others, including Actel, Quicklogic, and Atmel have worked with First Silicon Solutions as a debug tools partner to provide debug capabilities to their customers. FS2 Logic Navigator is designed to provide this logic analyzer function for embedded FPGA signals. Since many of these tools have similar features, we use can Logic Navigator ® as being of other logic analyzer features and operations as well. FS2 Logic Navigator ® is a Configurable Logic Analyzer System based on on-chip instrumentation (RTL) IP and external hardware and software. In principle, the on chip IP connects signals in the designer’s HDL code to (internal or external) trace memory where the signals buffered and then exported to a GUI where they can be examined. Trigger events and other configuration parameters can be set up by the designer to control which signals are recorded in memory and the conditions for capture. There are two major types of Logic Navigator systems; Trigger and trace memory may be either implemented inside the FPGA (Internal Logic Navigator) or implemented in a dedicated trace and debug probe (External Logic Navigator).
Figure 1: On chip Instrumentation based debug Logic Navigator consists of 4 components that provide a turnkey on-chip FPGA analysis solution
OCI blocks are provided as Verilog and VHDL models, which makes Logic Navigator implementation target independent. In operation, the OCI routes (user defined) internal signals that require analysis in the designer’s HDL code to a trace memory where the signals can be examined. Depending on Logic Navigator type, the trace memory may be external to the FPGA (External Logic Navigator Probe) or may use memory resources on the FPGA (Internal Logic Navigator). Logic analyzer selection depends on these user decisions about memory and IO available for probing, and what features (trigger events, trace width and depth) that are needed. External and Internal Logic Navigator configurations Basic questions a designer must address in adding debug to a design is analysis requirements - what signals that need analysis, level and type of trace needed, and tradeoffs - the amount of on chip resources, logic, memory and IO, that are available for debug use. Two approaches to logic analyzers are Internal (debug logic is contained on chip) vs. External (most debug logic is in the probe). Logic Navigator provides product options for both Internal and External operations. The Internal Logic Navigator inserts event recognition and control logic and trace memory into the FPGA design. The trace memory data and control logic to start, stop and read the trace memory is synthesized along with the user design. The benefit of this is that depending on Logic Navigator type, it only requires 2 to 4 external device pins on the chip, independent of how many signals are being traced, to implement a serial or JTAG interface, such as Actel’s FlashPro probes, to allow a zero overhead (no extra pins required) debug interface. The tradeoff is that On Chip resources are added at synthesis and are proportional to the number of signals being traced, trigger events and triggering features, and the depth of trace desired. The Internal Logic Navigator supports trace memory depth from 128 to 64K words. IN many cases, this trace depth is typically limited in general by the amount of available on chip RAM in a particular device.. Some versions of Logic Navigator also include the ability to directly set on chip register values via the JTAG interface, which is useful for setting designs into test or debug modes.
Figure 2: Internal Logic Navigator Instrumentation he External Logic Navigator minimizes the amount of on chip resources required for trace and triggering, at the expense of a larger off chip dedicated IO. The External OCI contains no on chip FGPA event recognition logic and uses no on-chip memory to trace data, which makes for an extremely low impact on requirements on the user’s design. Instead, all data is routed off-chip to the External Logic Navigator Probe, which contains event recognition logic enabling the designer to create up to 4 complex trigger events and trace memory allowing the designer to store 128K words of data.. The number of pins on the trace port is indirectly proportional to the number of signals being traced and the configuration selected and can range from 2 to 35 pins. For lower FPGA operating speeds, the External Logic Navigator support multiplexing compression of the data signals, so that, as an example 32 traced signals running at 50 MHz can be exported using 16 pins and at 25 MHz can be exported using 8 pins.
Figure 3: External Logic Navigator Instrumentation Integrating Logic Navigator into your design Adding new logic to a design is tedious and introduces the possibilities of adding new errors to a design. FS2 automates the integration and connect of the OCI to a design with an EDA tool called OCI Generator, that parses existing user designs RTL (hierarchical VHDL or Verilog) files, finds available signals for trace, and creates a new instrumented version of the RTL.
Figure 4: Logic Navigator Instrumentation Integration and Debug flow The instrumented RTL includes the OCI and its connection to the rest of the design. As in most tools, information gathered is only as usefulness and valuable as means of displaying it. Trace information is displayed in a logic analyzer GUI with both waveform and state display, cursor and trigger control, etc. as well as in a console view. All trace information from Logic Navigator can be saved for subsequent analysis or exported as a VCD file for use with other verification tools.
Figure 5: Logic Navigator GUI Using the Logic Navigator as part of System Debug Solution In complex FPGAs, logic analysis is only part of the debug solution. If a processor is part of the debug, the user has the added complexity of ensuring proper processor operations in addition to and coordinated with verifying their logic design. Most processors have their own debug interfaces and environments. A logic analyzer like Logic Navigator can be used both in conjunction with processor debug blocks and can to provide cross triggering between processors and logic to aid in more comprehensive debug. This cross triggering can be controlled by the Logic Navigator by trigger output s from the OCI or directly from the JTAG controlled registers.
Figure 6: Navigator Integration for System Processor Debug In summary, debug instrumentation is a very useful tool for any FPGA designer to have available and in cases is the only and most effective means of on chip analysis capabilities that are available. Logic Navigator is a vender neutral approach that can support all larger FPGA chip types, but other tools are available as well from FPGA venders, which may be more customized to their architectures. An Actel specific version of Logic Navigator, supporting all their FLASH based FPGAs is available for evaluation download from the FS2 website, www.fs2.com. by Neal Stollon, First Silicon Solutions, Inc.
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