Introduction

Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA software users, the same shrinking geometries that make their design problems tougher are also helping to improve the compute performance for their EDA tools.

But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping pace with device complexity? Because many new devices like 3G cell phones, internet routers, image processors, etc. require massive verification sequences that would take many CPU-years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software in order to fully verify a new SoC or system design.

Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a kind of chicken-egg problem: which comes first- the “final” hardware or the “final” software? Embedded software developers need an accurate model of the hardware in order to validate their code, while the hardware designers need fairly complete software to fully validate their ASIC or SoC. Software developers can sometimes get started using a bare-bones, cycle accurate model of the processor and an instruction set simulator (ISS). Similarly, chip designers can simulate their design along with small code snippets or diagnostics to verify basic functionality. But eventually both these groups need to come together on a common model to verify the complete hardware and the embedded software together. For most teams that first complete model is the actual silicon.

The problem with waiting for real silicon is that the embedded software can’t be fully validated in the context of a complete, accurate system model until very late in the design cycle. That increases

the probability that significant problems will be found in the silicon, the software or both, often necessitating additional silicon respin and code revisions. Both of these have significant cost and time-to-market implications. The costs can be substantial. At 90 nm, a new mask set costs approximately $1.5M and may add weeks to months of additional delay. What’s more, a 3 month delay in a fast–moving market can cause a loss of 25% of total product lifetime revenue, according to IBS, Inc. How can these costs be avoided? What’s needed is a hardware-assisted verification approach that can enable hardware/software integration to begin well ahead of first silicon.

Traditional Approaches to Hardware Assisted Verification

Logic emulation and FPGA prototyping have been around for more than a decade but neither of these approaches provides an optimum solution for hardware/software integration. Traditional emulation systems offer the large capacity required to emulate complex systems, in addition to hardware debugging features that help designers isolate bugs in their chip design. However they are very expensive assets, while their performance is just mediocre- often 500 KHz or less. As a result, these systems tend to be relegated exclusively to hardware verification activities, and mostly for large companies with big EDA budgets.

Embedded software teams typically need better performance to run long code sequences, and need more cost-effective systems since they may need multiple copies to support a team of several software developers. FPGA-based rapid prototyping systems are an order of magnitude faster than emulators and are much less costly. However, their capacity is typically limited to a few million gates and they are not well suited to hardware debugging tasks since probe points must be added selectively at compile time. As a result, FPGA prototypes appeal more to software development teams.

Introducing ZeBu- The Best of Both Worlds

What’s needed is a new approach to hardware-assisted verification that combines the strengths of traditional emulation and rapid prototyping into a unified solution that is accessible to both hardware designers and software developers. That’s what EVE has set out to do with the breakthrough architecture used in ZeBu (for Zero Bugs). As shown in the table below, ZeBu is much faster and more affordable than traditional emulation systems, and offers much higher capacity and better hardware debugging than FPGA prototyping systems.

ZeBu has been architected to meet the needs of both hardware and embedded software engineers, and provides them with the hardware and software debugging facilities they need to debug complex SoC designs. ZeBu incorporates the largest FPGAs available with the highest level of integration and smallest footprint- all key to the system’s capacity, performance and cost-effectiveness. The ZeBu compiler automatically handles logic clustering, clock tree mapping, and bus & memory modeling, making it easy to map even large designs into the emulator. These have historically been the biggest problems with other FPGA-based rapid prototyping systems, but not with ZeBu, thanks to its complete software infrastructure.

ZeBu’s patented Reconfigurable Test Bench (RTB) architecture makes the system especially well suited for hardware debugging applications. The RTB controls and optimizes how the emulated system receives stimulus and communicates with software running on the workstation. Based on a powerful C/C++ API, the RTB communicates directly with HDL test benches (VHDL/Verilog/SystemVerilog) and/or abstract system level models (C/C++ or SystemC™). The RTB supports communications both at the signal/bit-level and at the transaction-level with high-level data such as frames, packets, or blocks. The latter is an especially efficient and high speed means of communication between ZeBu and the software testbench. In addition, the RTB is used to implement complex synthesizable transactors, synthesizable test benches, and embedded software applications.

The RTB also provides all the controllability and observability functions required by hardware designers in order to debug their design. For example, the RTB provides interactive read/write access to all internal registers and memories at run-time, without needing to compile internal probes. It also includes a built-in logic analyzer to trace the test bench and the design states over long emulation runs.

ZeBu Applications

ZeBu’s flexibility enable its use throughout the hardware and embedded software development cycle to:

• Verify and debug ASICs/SoCs, IP cores
• Co-verify hardware and software
• Develop and debug embedded software

These applications are detailed below:

• Verify and debug ASICs/SoCs, IP cores

With its integrated hardware debugging resources and high execution speed, ZeBu is ideal for verifying and debugging complex hardware blocks, IP cores and full chip designs. Early in the design cycle Zebu can be used as a simulation accelerator in co-emulation with leading HDL simulators and/or C/C++ code. ZeBu can be driven by existing HDL testbenches with no modification, and by HVL testbenches such as Vera and e. In addition, test benches can be applied externally by the workstation or synthesized and mapped into the emulator.

• Co-verify hardware and software

Later in the design cycle as the pieces of the design come together, ZeBu can be used to validate the entire system by running the embedded software with either a synthesizable test bench or in co-emulation with C++/System C code on the workstation. ZeBu has been architected for especially fast co-emulation at the transaction level, with operating speeds up to 12 MHz. For software debugging, the system’s processor can be connected through a JTAG cable or transactor interface to standard embedded software debuggers from ARM, TI, ARC, etc. In this way ZeBu can execute software drivers, operating systems or applications at MHz speed, while providing full hardware and software debugging capabilities to both hardware and software engineers on the same design representation. This enables hardware and software development teams to collaborate on the resolution of integration issues in a way that was never possible before.

• Develop and debug embedded software

ZeBu can also be used as a dedicated software development platform for embedded software developers, with full access to software development and debugging tools. The embedded software can be downloaded into the design memory via the PCI interface in a fraction of second, much faster than via the JTAG port. Also, ZeBu’s save and restore capability can be used to skip the OS boot phase and advance directly to the point in the code at which a problem was detected. Since hardware debugging features are not required at this stage, EVE offers a “replicate” version of ZeBu that is optimized for the needs of embedded software developers, and available at a fraction of the cost of a full ZeBu system. In this way, large software development teams can share multiple ZeBu systems at a reasonable cost.

ZeBu Operating Modes

In order to provide the most value for each of these applications ZeBu supports several operating modes that help exploit Zebu’s performance throughout the design cycle. The 7 different operating modes are as follows:

Co-emulation with commercial HDL simulators: A co-emulation link connects ZeBu to any VHDL/Verilog simulator compliant with the IEEE Verilog PLI interface, such as NC-SIM™, VCS™ and ModelSim™. Specman Elite and Vera are also supported via the HDL simulator.

Co-emulation with Signal-level C/C++/SystemC: ZeBu provides a C/C++ API with which one can create efficient C/C++ test benches to stimulate the design under test at the cycle level. The C++ API also supports the connection to a SystemC model at the cycle/event level.

Co-emulation with Transaction-Level C++/SystemC: When the design under test includes bus interfaces (such as Ethernet, PCI, USB, Sonet…), it is possible to stimulate it with C++ test benches at transaction level (i.e. with high level data such as frames, packets or blocks) instead of at signal level to minimize the amount of data exchanged between the host PC and the ZeBu-XL board. The C++ API also supports the connection to a SystemC model at transaction level (through channels).

Test Vectors: This pattern-based mode accelerates the regression testing of designs before tape-out. A pattern file, captured during HDL or C/C++ co-emulation, can be played back at higher speed without the HDL simulator or the C/C++ test bench present. The pattern execution tool detects output signal differences between the expected responses and the current values provided by the emulated design.

Emulation with Synthesizable Test Bench: A synthesizable test bench can be embedded in the FPGA of the RTB to enable emulation at several MHz. This mode provides the best level of performance since there is no interaction with any external software or hardware components. EVE provides a catalog of synthesizable memory models from Micron and Samsung.

Emulation with Software Debugger Control. The emulated design can be connected via the Z-SmartICE interface to any software debugger via a JTAG cable or JTAG transactor. The debugger will then be in control of the software execution.

In-Circuit Emulation with Target System and/or Hard IP Cores: In this mode, the emulated design under test is cabled to the target system, which provides all stimulus and control. One or more hard IP cores can also be included in the system model and speed-bridges can connect the design to real-time interfaces. A built-in logic analyzer running at up to 12 MHz can trace the design states over long emulation runs. Complex triggers can be added to control the tracing mechanism.

Multi-mode Operation

ZeBu also supports combinations of the modes outlined above. For example, a multi-mode test environment could include a synthesizable test bench with a Micron DRAM synthesizable model, an in-circuit interface in the form of a PCI-X hardware bridge, a JTAG cable connection to a S/W debugger and an LCD transactor displaying the LCD image stream directly on the host PC.

Summary

Unprecedented device complexity and embedded software content are driving the need for a new hardware-assisted verification approach. ZeBu is a breakthrough architecture that combines the strengths of traditional emulation and rapid prototyping into a unified platform for both hardware and embedded software development. For the first time a single platform and design representation can satisfy the needs of both these applications, enabling hardware designers and software developers to communicate and collaborate in a way that was never possible before. The net benefit of ZeBu’s unifying approach is to accelerate hardware/software integration well ahead of first silicon, reduce unnecessary respins and software revisions, and shorten time to market.

With a highly cost-effective architecture, ZeBu makes emulation faster and more accessible than ever before - accessible to both SoC designers and embedded software developers, accessible throughout the design cycle, and accessible by groups with modest EDA budgets. Overall, ZeBu clearly provides the best return on investment of any hardware-assisted verification approach.

ZeBu is a trademark of EVE USA, Inc. All other company, product or service names mentioned herein are trademarks of their respective holders and should be treated as such. All rights reserved. ©2005 EVE USA, Inc.

February 24, 2005

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