Field-programmable gate arrays (FPGAs) have a well-established position in every systems engineer’s toolbox. Taking advantage of their flexibility, engineers have used FPGAs for many years to rapidly prototype systems or in low-volume pre-production applications. When the communications- and network-driven Internet bubble took off at the turn of the millennium, demand skyrocketed for FPGAs in higher gate densities at any cost. Since then, however, FPGA requirements have changed dramatically. Today, as companies increasingly focus on the bottom line, engineers look for silicon solutions that offer both low unit and low total system cost.

While ASICs have traditionally offered the lowest unit cost of any silicon solution at high volumes, escalating time-to-market pressures, exponentially increasing NRE (non-recurring engineering) charges and the rising need to mitigate risk are preventing them from addressing system designers’ needs. Instead, a new ASIC alternative, the value FPGA, has emerged to address engineers’ requirements for a technology capable of meeting today’s shrinking development cycles with a low cost structure. This paper will define this new value-based FPGA market and will detail the various FPGA-based ASIC alternative solutions available.

New Opportunity for FPGAs

Two factors are driving the rapid evolution of this new value-based FPGA market. The first is the accelerating decline in FPGA unit costs. Leveraging advances in semiconductor process technology and ongoing manufacturing efficiencies, FPGA vendors are now able to offer programmable devices at unit costs comparable to traditional ASICs. In many highly cost-sensitive markets where FPGAs have not been widely used due to higher unit costs, FPGA-based solutions are now reaching a breakeven point with ASICs

At the same time, skyrocketing ASIC NREs are driving up ASIC unit costs. Today it is common to see mask costs for a standard cell ASIC design run in the millions of dollars. As mask costs have risen, so, too, have the effective unit costs of ASIC solutions, particularly in projects running under 500K units, making comparably priced value-based FPGA alternatives increasingly attractive.

Market analysts’ projections of growth in the programmable logic market validate those trends. First, analysts predict the use of FPGAs will continue to grow dramatically. With a CAGR of over 15 percent, analysts expect the overall programmable logic market will nearly triple in size between 2002 and 2008. Second, analysts predict this growth will be driven by the rapid adoption of programmable logic within the automotive and consumer market segments. The use of FPGAs in consumer applications is forecast to grow to more than $1B by 2008, almost 10 times its 2002 revenue levels. Much of this growth will be fueled by the worldwide adoption of new digital and high-definition broadcast TV transmission standards, gaming and multimedia entertainment systems, LCD and plasma display technology, and the widespread use of home DVR and DVD-W technologies. In the automotive market, FPGAs will be increasingly used for in-cab entertainment systems and in-cab GPS navigation, information, communication, and safety systems. In both market segments, designers are turning to FPGAs for the unique advantages they offer in terms of rapid deployment and programmability and their growing availability at lower price points. Value FPGAs are also finding their way into many data and telecom cost-reduction programs.

Defining User Needs

Given the high growth rates forecast for this new market, FPGA vendors are aggressively positioning their technology as the best solution for these emerging applications. Many have begun promoting their products as the “World’s lowest cost FPGA” and “The ASIC alternative” technology. Clearly, this battle will be fought at ASIC price points. But, to successfully serve as an “ASIC alternative,” value FPGAs must demonstrate a unit cost price structure that is highly competitive with ASIC unit costs plus their NRE. This new class of FPGAs must offer ASIC-like price points of sub-$2, sub-$5, sub-$10 and sub-$20.

Moreover, FPGAs in this new market must also match many of the additional characteristics that have made ASICs attractive in high-volume applications. The ASIC-like features that will factor heavily in the “ASIC alternative” (value FPGA) decision-making process include: high performance, low power, security, reliability, live at power-up, single chip, small form factor, breadth of product offering and overall ease of use. It is important to note that with some FPGA technologies these additional capabilities are either not available or come at a cost. Accordingly, that additional cost must be factored into the overall unit cost of the solution.

Security and reliability are particularly interesting issues within the rapidly growing consumer and automotive electronics markets. For FPGA technology to be widely adopted in the consumer market, for example, designers must be able to use the technology to protect the profits of consumer equipment manufacturers (CEMs). The highly competitive nature of the consumer market and the high run rates of products make them highly attractive targets for theft. In a growing number of products, designers are implementing the easily replaceable portions of the product in standard, off-the-shelf parts while the value-added aspects of the system are embedded in FPGAs. The adoption rate of FPGAs in this market will depend largely on the ability of FPGA technology to protect those unique value-added features in a design. If a potential thief can steal a design by simply copying the FPGA code being loaded into an SRAM-based device, CEMs are unlikely to adopt programmable logic technology on a wide scale. So, in many ways, the security capabilities of an FPGA technology are more critical to the success of the product in this low-cost value FPGA application than they are in applications that use higher priced full-featured FPGAs.

In a similar way, customers in these two high-volume markets expect demanding levels of quality and reliability. Some FPGAs, specifically those based on SRAM technology, suffer from reliability problems associated with neutron-induced configuration errors. These so-called “firm errors,” while more prevalent at higher altitudes, are still a significant problem at commercial altitudes up to 5,000 ft above sea level. They can cause an SRAM FPGA’s design to change unexpectedly, leading to a system malfunction. Independent data has shown that firm errors are the predominant failure mechanism in SRAM-based FPGAs at all altitudes and that they have a failure rate up to two orders of magnitude higher than industry norms at commercial altitudes. In high-volume applications, such as those found in the automotive and consumer electronics market, ensuring product quality and reliability are key criteria for achieving market success and an issue that has to be addressed by the value FPGA product offerings.

Technology Options

FPGA vendors offer two fundamental technologies in this value FPGA market segment: flash FPGAs, such as the Actel ProASIC3 families, and SRAM-based FPGAs offered by other vendors. At a glance, it is easy to assume that these two FPGA technologies offer similar characteristics and capabilities. Both are in-system programmable, offer high-performance programmable logic, and are available in densities to 1M system gates and beyond. In reality, however, there are very significant differences between the two technologies.

Like an ASIC, the nonvolatile nature of the reprogrammable flash-based ProASIC3 devices provides key advantages over the volatile SRAM-based offerings. ProASIC3 FPGAs use a flash programming cell to control the gate of the switch within the FPGA fabric. Each switch has a single sense gate (the switch) and a single flash floating gate that controls the state of the switch. In contrast, SRAM-based FPGAs rely on a six-transistor SRAM element for switch control and a pass gate for the switch itself. Unlike flash-based ProASIC3 devices, the volatile SRAM FPGA programming element must be loaded from an external device at every system power-up. This difference means that flash-based FPGAs are single chip and live at power-up, which allows for significant board level cost savings.

From a system security standpoint, flash-based FPGAs are the only value FPGA technology that is secure, immune from firm errors and can support secure remote updates over public networks. This higher level of security offers better protection against theft of critical IP. The device’s firm error immunity reduces the CEM’s risk of product liability and increases system reliability. The ability to conduct secure remote updates allows the product developer to update the product after deployment and, in the process, support a subscription-based business model through remote updates for feature enhancement. This capability can also eliminate the need for expensive service-based “truck rolls” to fix problems in the field.

Moreover, the inclusion of a small nonvolatile memory (NVM) in the flash devices can serve as an enabling technology in many consumer and automotive applications. The NVM can be used to store encryption keys for secure communications or to support device serialization in set-top boxes for broadcast-based systems.

Cost Comparisons

The ProASIC3 flash-based FPGAs start at the industry’s lowest cost point — $1.50 (250K units). ProASIC3 supports four device densities with over 10 part package combinations for under $5 (500K). Seven densities of the device with over 20 package combinations are available for under $10 (500K). ProASIC3 has the lowest unit cost and the broadest product offering at ASIC-like price points in the value FPGA market. In comparison, SRAM-based solutions, at best, provide two to three device densities under $10 and only a single device at the sub-$5 ASIC-like price point.

To compete with the unit cost advantages that flash-based FPGAs enjoy, SRAM FPGA solutions must be implemented on the most aggressive process technologies. However, this aggressive use of process technology comes at the expense of total system cost. Designs using SRAM-based value FPGA solutions must add expensive board-level infrastructure to support the technology and, in the process undermine the cost competitiveness of the value SRAM FPGA.

FPGAs based on SRAM technology have always required additional support circuitry and value FPGAs are no different. Each SRAM-based FPGA requires a boot PROM or microcontroller to load the FPGA configuration data. To ensure system reliability, designers often add an SRAM power supply brown-out detection device. Moreover, many designs using SRAM-based FPGAs require a live at power-up CPLD (complex programmable logic device) to manage system start up, especially if a microcontroller is being used to load the SRAM FPGA.

SRAM-based FPGAs fabricated in the latest 90nm processes must also meet stringent specifications on power-up as well as tight power supply tolerances which often require costly supply sequencing devices to manage power to the part. In many applications, external clock distribution devices must handle system clock management because the SRAM FPGA’s power-up configuration delay makes the device’s internal PLL/DLL circuitry unsuitable for this important system-level task. In all, a “value” SRAM-based FPGA may require anywhere from $3 to $20 of support circuitry. Accordingly, that additional cost must be factored in to determine the value SRAM-based FPGA’s true cost. The SRAM system overhead penalty can easily be over 100 percent of the SRAM FPGAs unit cost price without looking at the soft costs or reliability, inventory management and design complexity issues.

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