CURRENT FEATURE ARTICLES

Not Bad Die
Xilinx EasyPath Explained (Kevin Morris)
Avoid FPGA Project Delays by Adopting Advanced Design Methodologies
by Alex Vals, Mentor Graphics
40nm Altera Stratix IV
Bigger and Cooler than we Expected (Kevin Morris)
High-Speed Serial Comes to the Analog/Digital Divide - Lattice and Linear Technology Collaborate on JESD204 (Bryon Moyer)
Golden Hammer
Pursuit of the Programmable Panacea (Kevin Morris)
Playing Pin Twister
Taray Attempts to Untangle FPGA Pin Assignment
(Bryon Moyer)

JOURNAL WEBCASTS

NEW!! CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

[click here for more webcasts]

Not Bad Die
Xilinx EasyPath Explained
(Kevin Morris)

We always thought we knew how it would go down.

Under cover of darkness, our black-clad insertion team would rappel down the walls of the super-secret Xilinx fortress in the desert.  With the kind of precision timing and teamwork found only in movies and editorial feature introductions, we’d scan the perimeter and locate the vulnerable point.  A diamond-tipped drill bit driven by a silent motor would bore a hole just large enough for our fiber-optic viewing tool, and the telling video would be immediately beamed back to FPGA Journal headquarters.  At the same time, however, we’d inadvertently trigger the alarm system, and our squad would fragment, running for cover.  In a panic, our leader would end up like Charlton Heston, running for his life through the streets shouting, “EasyPath is Bad Die!  EasyPath is Bad Die!” [more]

Avoid FPGA Project Delays by Adopting Advanced Design Methodologies
by Alex Vals, Mentor Graphics

Introduction
Over two-fifths of FPGA design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification and production but also in the design process. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery.

For FPGA design, there are several methodologies that can be adopted to make life easier for both design and verification engineers. Two of these will be examined here: SystemVerilog for design and behavioral modeling. [more]