CURRENT FEATURE ARTICLES

40nm Altera Stratix IV
Bigger and Cooler than we Expected
High-Speed Serial Comes to the Analog/Digital Divide - Lattice and Linear Technology Collaborate on JESD204 (Bryon Moyer)
Golden Hammer
Pursuit of the Programmable Panacea (Kevin Morris)
Playing Pin Twister
Taray Attempts to Untangle FPGA Pin Assignment
(Bryon Moyer)
How To Implement SystemVerilog for FPGA Design
by Ehab Mohsen, Mentor Graphics Corporation
Merging with Agility
Alliance Unlocks FPGA Potential (Kevin Morris)

JOURNAL WEBCASTS

NEW!! CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

[click here for more webcasts]

40nm Altera Stratix IV
Bigger and Cooler than we Expected
(Kevin Morris)

New process nodes have a predictable rhythm.  Until about 90nm, we knew before anybody announced anything that we’d get double the density, half the power (dynamic, of course), and 50% more speed than we had in the previous generation.  Of course, that made waiting for the announcements from semiconductor companies a little less than suspenseful.  Our Moore’s Law alarm clock would beep on its two-year cycle.  We’d check to see if anybody had announced the thing we were expecting yet, and then we’d hit the one-month snooze button and fade back off into our dazed delirium.

This week, Altera became the first to announce an FPGA family on the 40nm process node, and the results surprised us.  (Editor’s note:  FPGA Journal was actually the first to announce 45nm – see “45nm Chicken,” but Altera outfoxed us by chipping off 5 more nanometers and turning their amp down to “40.”  The result is a future family that surprised us a bit, and it challenges classical definitions of the boundaries of programmable logic.

We didn’t know exactly what to expect at this process node.  Our predict-o-meter lost its punch at about 90nm where at least a modicum of drama crept into the scenario.  We’d watched the supply voltages step down from the 5V to the 1V range.  This meant that the voltage swings were less with each node, and the obligatory dynamic power savings came along pretty much for free.  Even though we were clocking more gates faster, the total power stayed the same or even dropped a bit due to the process technology gains.  While we weren’t paying attention, however, those transistors got leakier as they got smaller.

It was no big deal at first, but over time we began to see static power consumption due to leakage account for a measurable part of the total power.  At 90nm, this effect officially hit the map.  For programmable logic, it hit hard.  All those configuration transistors that complete the routing and define the LUT functions were not-so-quietly sucking up beaucoup current, raining on our power parade in a big way.  Other types of devices with metal-based fixed interconnect didn’t have this bloat, and therefore they could wait a generation or two before the static power problem hit like a tidal wave. [more]