FROM
THE EDITOR
Do you have a full-time intern whose job is nothing but typing hundreds of pin assignments for your FPGA design into an Excel spreadsheet, then schlepping the resulting document back and forth between you and the board design team? Maybe you need to read Bryon Moyer’s latest feature. Bryon looks at Taray’s solution to pin assignment management – a welcome addition to our arsenal of FPGA-on-board design tools.
Also this week, Ehab Mohsen of Mentor Graphics tells us more about how to use SystemVerilog for FPGAs. With the complexity of today’s high-end FPGA designs, advanced design languages are no longer “overkill”. This contributed article explains.
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Playing Pin Twister
Taray Attempts to Untangle FPGA Pin Assignment (Bryon Moyer)
Once upon a time, PLD pinouts were an easy thing. Oh, yeah, sorry… for you neophytes, that’s “Programmable Logic Device,” a term once ubiquitous, and still relevant, except that FPGAs are the overwhelmingly dominant survivor. So much so that some people think of PLDs as just the small non-volatile glue-mop-up devices, to paint an ugly mixed-metaphorical picture, even though an FPGA is no less programmable a device. Back in the day, when you were writing your Boolean equations in PALASM for your PAL16L8 (OK, I know I’ve lost a generation of you now), you simply listed the mnemonics you were going to use for the pin names on all 20 pins in order. Yeah, only 20… remember SKINNYDIP packages? (You youngsters can stop blushing now; we were a wild generation, work it out with your therapists.)
Contrast that with today’s megamonolithic monster FPGAminators that have over 1000 pins. List those babies. Oh, and there’s no obvious pin order; they’re in a grid. And they may operate at various voltages. Or they may have different I/O standards. And they’re organized in banks. And each bank may be associated with a specific power level. And you can’t necessarily mix arbitrary I/O types in a bank. Oh, and depending on the I/O standard being used, you can only have so many outputs within a bank, and they have to be within a certain number of pins of a ground to avoid issues with simultaneously switching outputs (variously called SSO, ground bounce, silent low by the various generations that thought they invented the concept). (No, you young whippersnappers, I’m not having a maturity meltdown...)
[more]
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How To Implement SystemVerilog for FPGA Design
by Ehab Mohsen,
Mentor Graphics Corporation
Introduction
Since its ratification in 2005, the SystemVerilog IEEE-1800 standard has experienced broad adoption in the verification and assertion space but has lagged for design constructs. Engineers may be wary of revamping current design methodologies, or they assume that SystemVerilog for design is not relevant to their projects, or they fear that field-programmable gate array (FPGA) synthesis tools do not fully support the new standard. All three of these concerns are either exaggerated or based on misconceptions. SystemVerilog is fully supported by leading synthesis tools, and the new design constructs are in fact relevant to most register-transfer level (RTL) coding styles and easy to learn and integrate into current methodologies. [more]
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