CURRENT FEATURE ARTICLES

Merging with Agility
Alliance Unlocks FPGA Potential (Kevin Morris)
Synplicity Gets Spirit
ReadyIP Announcement has Bigger Implications
(Kevin Morris)
One to Many
FPGA Design Diversifies (Kevin Morris)
Tools and Transceivers
Dual Xilinx Announcements (Kevin Morris)
Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations
(Bryon Moyer)
Synthesis Flows Back to the Sea
Synopsys Buys Synplicity (Kevin Morris)

JOURNAL WEBCASTS

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age-DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK CES 2008. Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now!

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier. Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

[click here for more webcasts]

Merging with Agility
Alliance Unlocks FPGA Potential
(Kevin Morris)

We’ve talked many times about the potential of FPGAs in providing incredible amounts of the Good kind of power (computing) while consuming comparatively tiny amounts of the Bad kind of power (“juice”).  When you want a lot of numbers manipulated very quickly with the least possible amount of juice, a highly parallelized datapath implemented in the programmable fabric of an FPGA is hard to beat.  That’s why we have groups like the die-hard fringe of supercomputing – the “reconfigurable computing community” struggling for decades to build a tool infrastructure that can more easily get more of those big ’ol algorithms squished down into FPGAs. 

As we’ve pointed out many times, one of the most demanding applications for FPGA-based datapath acceleration is DSP (or any algorithms with DSP-like properties in areas like video processing).  FPGAs today come loaded with DSP-specific blocks like hardware multipliers or multiply-accumulate (MAC) units.  While the FPGA companies’ “maximum performance” specifications are mostly a joke (they multiply the number of MAC units by the maximum frequency and come up with a GMACs [Giga Multiply-Accumulates per second] number that’s far north of anything a real design could possibly achieve), the real-world performance results are still amazing.

What hasn’t yet become amazing is the simplicity of the design flow required to get a complex datapath algorithm into FPGA hardware or, more realistically, into a combination of embedded software and FPGA-based hardware accelerators.  Most DSP designers start with their favorite tools from The Mathworks – MATLAB and Simulink.  MATLAB provides a near-ideal environment for basic algorithm development and refinement, and Simulink facilitates model-based design and adds a few more features of particular interest to hardware designers.  Of course, it also comes with a much bigger price tag.  This proves that the group of people bright enough to bring the world MATLAB is also bright enough to know that typical commercial electronic design projects have much bigger budgets than the typical college math professor.

We have discussed a number of DSP development flows that revolve around model-based design with Simulink, but very few that exploit the power of language-based design at that level of abstraction.  Earlier this year, two of the companies focused on development of high-performance hardware/software systems for DSP design – Celoxica and Catalytic, came together to form a new company – Agility.  Agility will focus on taking algorithms from MATLAB to implementation in a combination of hardware and software.  Catalytic already had a strong portfolio of tools for signal processing design, verification, and implementation, and the addition of Celoxica’s C-to-FPGA tools rounds out the solution so that ultimately a clean tool flow will take algorithms from MATLAB to C and FPGA hardware.

When starting from the freeform world of MATLAB, a lot of things need to be nailed down before we can get to something that is correctly described either in C that can be executed on an embedded processor or in a hardware description that can be implemented in FPGA fabric.  On the software side, MATLAB kindly protects us from issues like dynamic memory allocation, strong typing of variables, vector vagaries, and a host of others.  When we want to take MATLAB code into something we can successfully execute in C on a typical embedded system that perhaps doesn’t allow dynamic memory allocation, it gets a little more challenging.  [more]