CURRENT FEATURE ARTICLES

Synplicity Gets Spirit
ReadyIP Announcement has Bigger Implications
(Kevin Morris)
One to Many
FPGA Design Diversifies (Kevin Morris)
Tools and Transceivers
Dual Xilinx Announcements (Kevin Morris)
Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations
(Bryon Moyer)
Synthesis Flows Back to the Sea
Synopsys Buys Synplicity (Kevin Morris)
Maximizing Your Millimeters²
Actel Expands Low Power Line

JOURNAL WEBCASTS

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age-DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK CES 2008. Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now!

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier. Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

[click here for more webcasts]

Synplicity Gets Spirit
ReadyIP Announcement has Bigger Implications (Kevin Morris)

While the word “ecosystem” is happily bantered about by major FPGA vendors, history would indicate that FPGA companies are less than perfect participants in the care and feeding of “ecosystems” to support their products.  The turmoil associated with the love/hate, competitor/partner, customer/supplier relationships between FPGA companies and others providing various products and services to the FPGA community are well documented. 

Commercial EDA companies are a perfect case-in-point.  While trying to make a business creating and selling design tools to FPGA designers, they need to cooperate closely with FPGA companies in the creation of their tools and supporting libraries, and then they have to compete with those same FPGA companies who are providing competitive tools directly to their customers at virtually no cost.

EDA companies have always relied on two arguments to justify customers’ investments in their third-party tools instead of the FPGA vendors’ offerings – better tools and vendor independence.  The “better tools” differentiator is a constant race – EDA companies have to sprint to keep their tools ahead of the FPGA vendors, and the FPGA companies are constantly catching up.  Compounding that effect – when an EDA company introduces a new feature, it is never long before that same capability shows up in an FPGA vendor’s tool.  We’re not talking about patent violations here – just a “fast follower” strategy on the part of FPGA companies trying to compete with each other by offering as close as possible to commercial-grade tools in their almost-free standard offerings.  Nonetheless, top-flight EDA providers like Altium, Mentor Graphics, and Synplicity have managed to keep their offerings one (or three) steps ahead of the vendors’, keeping their tool businesses intact.

The second argument – “vendor independence” has always been on shaky ground.  While it sounds nice in concept to have your designs and design tools easily retargetable from one vendor to another – say, if vendor “B” suddenly announces a newer, cheaper, faster part than the one you started with, that vision has never really been very practical.   One of the biggest obstacles to vendor-independent design is IP.  If you throw down some common peripheral like a PCI core (or these days, a microprocessor), you may save yourself a lot of design work, but you’ve just locked your design forever in the silicon of the vendor whose IP you chose.  FPGA companies know this, and they invest a lot in building vast libraries of IP that they make available for a pittance. 

Sometimes, this vendor-supplied IP is not easy to remove from your design once you’ve designed it in.  For example, if you include a proprietary processor core in your FPGA design and then write a bunch of processor-specific software based on that architecture – it won’t be a trivial change to remove that processor and replace it with an alternative if you want to jump to a different FPGA supplier.  The solution to this “sticky IP” problem is vendor-independent IP – the kind that people want to sell for money.

In the ASIC arena, commercial IP has been big business for a while now.  Licensable IP can dramatically reduce design and verification cycles and can also significantly improve design parameters like power, performance, and cost.  IP that has been engineered and proven over years of commercial use is almost always better than what your team will whip up in their spare time – particularly for non-differentiating functions such as standard interfaces.  It is a rare product that beats out the competition because its USB interface is more elegant. [more]