FROM
THE EDITOR
Think you know how to do an FPGA design? More and more people are jumping on the FPGA bandwagon, and each new group brings a new dialect to the region. Before you know it, there will be more different ways to blast bitstreams into FPGAs than we ever imagined. Our latest feature has the details.
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Kevin Morris – Editor in Chief
Techfocus Media, Inc.
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One to Many
FPGA Design Diversifies (Kevin Morris)
About a decade ago, FPGA design followed in the footsteps of ASIC and went language-based. For a very long time, the only question we asked ourselves was “VHDL or Verilog?” It was reminiscent of the “Paper or Plastic?” scenario in the grocery checkout line. Gradually, however, people sneaked into the FPGA-designing fold that weren’t FPGA designers. Who are these folks anyway? We’ve got DSP engineers, embedded systems designers, board designers, supercomputing folks… the list goes on and on.
Apparently all those new engineers didn’t get the memo about conforming to our established design methodologies, or else they just didn’t feel like becoming experts in VHDL and Verilog. Compounding the problem was the fact that FPGA and EDA companies – money-grubbing monsters that they are -- decided to actually cater to these interlopers by giving them gold-plated, easy-as-pie design entry mechanisms that allowed them to almost completely forego the time-honored traditions of entities and architectures.
If, for whatever reason, you don’t want to hand code each and every line of your field-programmable masterpiece, you now have abundant options for populating your LUTs with logic of alternative origin. Thanks to all these HDL-phobic pansies, we now have a variety of fun, interesting, sometimes dubious ways to create working FPGA designs without really working on FPGA design. Let’s take a survey of some of the many methods available and emerging for harnessing the power of programmability without dedicating ourselves to the high art of HDL mastery.
Fundamentally, most of the approaches are based on design re-use. If somebody’s already coded up the block we need, (and we’re not stricken by terminal acute NIH syndrome) we are probably better off re-using their code rather than re-inventing the wheel, or the PCI interface, or… you get the idea. Every FPGA vendor has a library of IP that we can use to round out our design, saving us time we can use to focus on the original bits of our design – the parts that will add value and differentiation when our product goes to market. If you want some of the more advanced stuff, you’ll probably have to pay a bit to license it, but most of it is either free or very inexpensive – FPGA companies don’t want to put up any barriers to our using the maximum possible amount of their silicon.
Beyond the general-purpose IP supplied by FPGA companies, there are a variety of vendors that have more specific, higher-value blocks we can license for FPGA use. A few years ago there was a divide between ASIC-appropriate and FPGA-appropriate IP, but today almost all IP intended for ASIC use will at least work in FPGA because most ASIC designs are prototyped and verified in FPGAs before they go to ASIC tapeout. This means that the rich IP libraries from companies like Synopsys contain mostly FPGA-friendly IP. [more]
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