CURRENT FEATURE ARTICLES

Maximizing Your Millimeters²
Actel Expands Low Power Line
Comparing Power Consumption of FPGAs with  Customizable Microcontrollers
by Koji Gardiner, Stanford University
Making FPGAs Cool Again – Part 2
How Tools Unlock the Hardware Power Capabilities
(Bryon Moyer)
Passing the Torch
Xilinx Leadership Legacy Lives On
Making FPGAs Cool Again – Part 1
(Bryon Moyer)
Reconfigurable Computing for Acceleration in HPC
by Michael R. D’Amour, DRC Computer Corporation
Zero Power for Zero Dollars
Actel Breaks the Buck Barrier (Kevin Morris)

JOURNAL WEBCASTS

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age-DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK CES 2008. Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now!

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier. Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

[click here for more webcasts]

Maximizing Your Millimeters²
Actel Expands Low Power Line

FPGAs have always benefited from the rising waterline of Moore’s Law.  When the first programmable devices hit the market, the price of programmability was very high.  The amount of density, power, and performance you gave up to gain the privilege of programming your hardware on your desktop or in your system was so large that only a few specialized applications could justify the programmability penalty.  As process nodes passed, however, Moore’s Law worked in our favor.  As transistors got cheaper, faster, and thriftier on power, the relative disadvantage of FPGAs disappeared for more applications, and the market broadened.

Actel has surfed a similar wave when it comes to non-volatile flash-based FPGAs compared with traditional SRAM-type devices.  Flash-based FPGAs have always offered certain attractive advantages – very low static power, single-chip operation, live-at-power-up simplicity, high radiation tolerance, and good design security.  However, the penalty box included some often show-stopping biggies like lower density (and thus higher cost) and lower performance.  In recent times, however, flash-based FPGAs have gained enough relative ground that they can meet the density, feature, and performance targets of many more applications – thus their advantages come into play and differentiate them. [more]

Comparing Power Consumption of FPGAs with  Customizable Microcontrollers
by Koji Gardiner, Stanford University

Introduction
As transistor technology quickly shrinks toward the vanishing point, embedded devices are taking over the marketplace.  One of the key challenges of designing an embedded electronic device is maintaining reasonable power consumption in order to maximize battery life.  For design engineers wanting to combine the functionality of a microcontroller with their own “special sauce” logic, a standard off-the-shelf microcontroller plus Field Programmable Gate Array (FPGA) combination has long been the preferred option.

Despite the ease of use and availability of FPGAs, they are notoriously power hungry and can quickly overwhelm the power budget of an embedded system. [more]