CURRENT FEATURE ARTICLES

Making FPGAs Cool Again – Part 2
How Tools Unlock the Hardware Power Capabilities
(Bryon Moyer)
Passing the Torch
Xilinx Leadership Legacy Lives On
Making FPGAs Cool Again – Part 1
(Bryon Moyer)
Reconfigurable Computing for Acceleration in HPC
by Michael R. D’Amour, DRC Computer Corporation
Zero Power for Zero Dollars
Actel Breaks the Buck Barrier (Kevin Morris)
SystemVerilog is Coming to FPGA Design
by Daniel Platzker, Mentor Graphics
45nm Chicken
We Win (Kevin Morris)

JOURNAL WEBCASTS

NEW!! CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

NEW!! Approaching Yield in the Nanometer Age. This tutorial goes into detail on DFM technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. (Mentor Graphics)

NEW!! CHALK TALK CES 2008. Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now!

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier. Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications. Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

Making FPGAs Cool Again – Part 2
How Tools Unlock the Hardware Power Capabilities (Bryon Moyer)

A couple weeks ago we looked at the state of FPGA low-power design from the standpoint of hardware. We saw a range of features, from very little to branded feature sets. But none of that matters without tools: tools are the window into the silicon, and no silicon feature has a shred of value unless a tool uses it (as can be testified to by the scores of now-defunct PLD businesses that were run by “the cheapest silicon always wins and software is annoying” types). And with a domain like low-power design, the tools can have features on their own even if there are no explicit hardware features to exploit: more intelligent use of plain-vanilla silicon can reduce power as well.

So this week we look at the ways in which various FPGA vendors have addressed the power problem in their tools. There are really two parts to that story: analysis and synthesis. It doesn’t make sense to try to design for low power if there’s no way to see how much power you’re consuming. [more]