FROM
THE EDITOR
This week, Bryon Moyer is back with a big feature that just wouldn’t fit in one issue. “Making FPGAs Cool Again - Part 1” is the first installment of a two-part power extravaganza. Power is becoming one of the most important FPGA design criteria these days, and despite all the efforts by marketing to make us think that power efficiency simply falls from the clouds when we pick the right FPGA, optimizing design-for-power still comes from good old-fashioned high-quality engineering. Go figure!
Our second feature looks at another rapid-growth FPGA application – reconfigurable computing (which is really another power issue in disguise). You see, when supercomputer installations have to pick a location based on where the power utility company can deliver the most current safely and efficiently, people start to care about computational power efficiency. Properly used, FPGAs can provide impressive compute acceleration at a tiny fraction of the power budget of vast arrays of conventional processors. Our latest contributed article from DRC has the details.
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Making FPGAs Cool Again – Part 1
(Bryon Moyer)
It was a demonstration that buzzed around the (admittedly small incestuous) industry. A digital clock being powered by a grapefruit. It’s the kind of thing you might see on the Discovery Channel these days, but back in the day, Phillips/Signetics created a local stir with their comparatively ultra-low-power CPLDs. At that time, it was competing with the incumbent PALs that drew about 180 mA of current (and competing with their half- and quarter-power versions made possible by CMOS encroaching on an erstwhile bipolar domain). As the smaller devices became commoditized, the spotlight moved to FPGAs, and data sheets stopped including ICC as a parameter with a hard limit. The official (and actually an accurate) explanation was that the amount of current drawn was too design-dependent, and that a “global” maximum current would be way way higher than anything a real design would experience. The more skeptical engineers were suspicious that it was just a way not to be accountable for power.
Whatever the reason, power became a non-issue for many years. FPGAs were going into communications and other rapidly-evolving systems for the purpose of speeding product to market. Systems designers were trading off power, cost, and even the ultimate possible performance in order to be able to ship their products as early as they could. Time to market was king; for everything else, good enough was good enough. [more]
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Reconfigurable Computing for Acceleration in HPC
by Michael R. D’Amour, DRC Computer Corporation
There has been significant research to support the potential performance gains available through the use of reconfigurable hardware for certain classes of computationally-intensive tasks. However, despite well-known advantages, the technology has historically struggled to gain a strong foothold in the high-performance computing (HPC) marketplace. While there were many reasons for this lack of early widespread acceptance, one major issue has been a lack of standards surrounding reconfigurable processors and the absence of a standardized system architecture that can effectively employ them.
Many of the technological barriers to widespread use of reconfigurable computers have been overcome, and with standards-based reconfigurable interfaces and hardware plus a growing body of standard language compilers to support the technology, reconfigurable computing is poised to break through as a viable solution for a wide range of commercial and HPC applications. [more]
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