FROM
THE EDITOR
This week, Actel launched a couple of new FPGAs that have the distinction of being the first to crack the $1USD barrier. At 99 cents each, you can buy three or four of these babies for the price of a good cup of coffee. OK, really you’d probably have to buy way more than three or four to get that price, but the total power will be far less than it takes to brew that shot of espresso. Our latest feature has the details.
Next, we have a contributed article from Daniel Platzker of Mentor Graphics telling us that SystemVerilog is becoming a viable option for FPGA design. For years, SystemVerilog has been “just around the corner” as a practical design entry language. Today, the tools and infrastructure are finally emerging that may bring the promise to reality.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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EVENTS & ANNOUNCEMENTS
The lowest power, low cost Actel IGLOO™ FPGA
Lower your power and stay in budget with the new 15k gate member of Actel’s IGLOO™ flash FPGA family. At only 5µW, the industry’s lowest power FPGA has 200x less static power than competitive FPGA offerings and more than 10x the battery life than PLDs in portable applications. All for only 99 cents!
 Learn more.
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Zero Power for Zero Dollars
Actel Breaks the Buck Barrier
OK, we have to come clean right away. In introducing their new 99 cent FPGAs (yep, not a typo), Actel never claimed that they were zero dollars or zero power. FPGA Journal is adding that part via a superpower we call “editorial license.” Here’s how it works – some of Actel’s competitors have already called their competing parts “Zero Power” because they have a static power consumption of less than a milliwatt. Apparently, the old ammeters would just show zero when the current dropped into the microamps, and some enterprising marketing dudes decided that was zero enough for them. We have explained all this in previous articles, of course, so here we’ll just say that it amounts to rounding down. Since Actel’s devices are even lower power than the “Zero Power” competitors, that one isn’t much of a leap. Also, as long as we’re rounding down, a 99-cent device would be zero dollars, right? Q.E.D. [more]
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SystemVerilog is Coming to
FPGA Design
by Daniel Platzker,
Mentor Graphics
Introduction
Since its introduction in 2005, SystemVerilog has been touted as the way to marry design and verification into a single language, enabling design with verification. Despite its blending of the best of Verilog, assertion languages and VHDL, SystemVerilog adoption has been slow — as with any new HDL or design methodology. But the language’s popularity is growing as tool support has improved, starting first with verification teams then expanding to ASIC designers and now also FPGA designers.
[more]
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