CURRENT FEATURE ARTICLES

45nm Chicken
We Win
Effectively Using Internal Logic Analyzers for Debugging FPGAs
by Brian Caslis, Lattice Semiconductor Corporation
State of the Union – Addressed
Major Players Weigh in on FPGA
Moving Data with VME
by Bryon Moyer, FPGA Journal
Pumping up Premier
Synplicity Boosts Flagship Tool
Incremental Design Moves Towards Mainstream
by Bryon Moyer, FPGA Journal
Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools
by Rakesh Jain, Mentor Graphics Corp.

JOURNAL WEBCASTS

CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier - Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes - Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems.
(Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

45nm Chicken
We Win

The swamp screams loudly around the abandoned road as the jousters position themselves for their impending bout.  Somewhere, in the back of their alcohol-soaked brains, they visualize themselves as medieval warriors mounting their steeds in a duel of chivalrous wit.  In the real world, their decrepit death-trap pickup trucks are a far cry from the mounts they mentally mimic, and the assembled audience of mosquitoes, flies, and the occasional bullfrog hardly constitutes the cheering throngs envisioned by these imbecilic soldiers of the sullen South.

With a final swig from their respective flasks of courage and a hearty “Yeee Haaa!!!” [more]

Effectively Using Internal Logic Analyzers for Debugging FPGAs
by Brian Caslis, Lattice Semiconductor Corporation

Factors Driving Change in FPGA Debugging Techniques
The ability to reprogram an FPGA has been a key benefit during the functional debug of a hardware design.  If the design is not working correctly, the ability to add “debug hooks” has been used by engineers since the earliest use of CPLDs and FPGAs.  Initially, signals internal to the FPGA that needed to be observed were brought out to pins and then external logic analyzers were used to capture the data.  However, as design complexity and size have increased, this approach is no longer adequate for several reasons. [more]