CURRENT FEATURE ARTICLES

Pumping up Premier
Synplicity Boosts Flagship Tool
Incremental Design Moves Towards Mainstream
by Bryon Moyer, FPGA and Structured ASIC Journal
Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools
by Rakesh Jain, Mentor Graphics Corp.
Actel Powers Down – Again
New ProASIC3L Family
Spreading the Span
ChipX Rolls Hybrid ASIC
Auld Langxiety
Bracing for 2008

JOURNAL WEBCASTS

NEW!! CHALK TALK Meeting The Challenges of FPGA Design With Synplify Premier - Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes - Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems.
(Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

CHALK TALK Did you miss the ARM Developers' Conference?  Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Xilinx Virtex-5 Power Optimization & Power Design Guidelines (Xilinx)

Virtex-5 FPGAs and PlanAhead Deliver Maximum Performance (Xilinx)

Accelerate Delivery of Built-in Ethernet Solutions Using ilinx FPGAs and Gigabit Ethernet Development Kit (Xilinx)

Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA (Xilinx)

Discover How the Complete Virtex-5 PCI Express Solution Reduces Risks for Your Application (Xilinx)

An Introduction to the Xilinx Virtex-5 FPGA Family (Xilinx)

Addressing Size, Weight, and Power Constraints (Altera)

Enable High-Volume Applications with New Low-Cost FPGAs (Altera)

Implement PCIe, GbE & SRIO with Altera's Low-Cost FPGAs (Altera)

Pumping up Premier
Synplicity Boosts Flagship Tool

With excellent tools available almost for free from FPGA companies, you might wonder why top notch design teams still pay for high-end FPGA tools from companies like Synplicity.  This week, Synplicity helped us out with that question with new improvements to their top-of-the-line synthesis offering – Synplify Premier.  Premier is now updated with new capabilities, and -- probably more important – support for the industry’s latest, biggest, baddest FPGAs, including Xilinx’s Virtex-5 family, and beta support for Altera’s Stratix III, Stratix IIGX, and Stratix II families.

Synplicity’s Synplify Premier has a technology called “graph-based physical synthesis” that is designed to help you reach timing closure faster – or on more complex designs, to help you get there at all.  As we’ve discussed before, delay in FPGAs has changed over the past several years and process generations.  Back at the larger geometries, most of the delay was in the logic elements themselves.  Because of that, logic synthesis could make a pretty good guess at delay just by adding up the known delays of all the logic elements in a path.  [more]