CURRENT FEATURE ARTICLES

Incremental Design Moves Towards Mainstream
by Bryon Moyer, FPGA and Structured ASIC Journal
Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools
by Rakesh Jain, Mentor Graphics Corp.
Actel Powers Down – Again
New ProASIC3L Family
Spreading the Span
ChipX Rolls Hybrid ASIC
Auld Langxiety
Bracing for 2008
New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support
by Daniel Platzker and Jaggi Balasubramanian, Mentor Graphics

JOURNAL WEBCASTS

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes - Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

CHALK TALK Did you miss the ARM Developers' Conference?  Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Xilinx Virtex-5 Power Optimization & Power Design Guidelines (Xilinx)

Virtex-5 FPGAs and PlanAhead Deliver Maximum Performance (Xilinx)

Accelerate Delivery of Built-in Ethernet Solutions Using ilinx FPGAs and Gigabit Ethernet Development Kit (Xilinx)

Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA (Xilinx)

Discover How the Complete Virtex-5 PCI Express Solution Reduces Risks for Your Application (Xilinx)

An Introduction to the Xilinx Virtex-5 FPGA Family (Xilinx)

Addressing Size, Weight, and Power Constraints (Altera)

Enable High-Volume Applications with New Low-Cost FPGAs (Altera)

Implement PCIe, GbE & SRIO with Altera's Low-Cost FPGAs (Altera)

Incremental Design Moves Towards Mainstream
by Bryon Moyer, FPGA and Structured ASIC Journal

I have this recurring nightmare. I’m supposed to write a chapter for a book. I’ve pretty much got it done, doing some final editing on the last paragraph, and then on review realize that the first paragraph has changed mysteriously. So I fix it, but then another paragraph changes. I never seem to be able to get all the paragraphs right. And then someone else submits his chapter, and for some reason my chapter gets all screwed up. Of course, that’s about the time I also realize that I forgot that I had signed up for a college class that, of course, I never attended, and the final is tomorrow, and I wake up in a cold sweat. [more]

Three “I”s of FPGA Design: Iterations, Incremental and Intelligent Design Tools
by Rakesh Jain, Mentor Graphics Corp.

The flexibility offered by field-programmable gate arrays (FPGAs) has made design iterations an integral part of the FPGA design process. Traditionally, engineers quickly wrote hardware description language (HDL) for their design, ran synthesis and place-and-route on it, programmed the FPGA and tested design functionality directly in hardware. If a performance issue or a functional bug was discovered, appropriate modifications were made to the HDL, followed by re-synthesis and re-place-and-route to obtain a new FPGA bit-stream and re-testing the hardware. This flow was fast enough to easily allow a few iterations in one day. [more]