The search for the best DSP solution for a given application usually leads designers into a maze of price, performance, and power consumption trade-offs, often requiring a compromise of one or more to accommodate the others. With the introduction of Spartan™-3A DSP, the latest addition to the Xilinx® XtremeDSP™ portfolio and the first Spartan FPGA to be DSP optimized, Xilinx has broken through the maze to deliver the most efficient combination of these three critical values for a host of applications, including wireless base stations, mobile defense communications systems, surveillance, automotive, video, and medical imaging technologies.

Spartan-3A DSP delivers 32 or more GMAC/s (32 billion multiply accumulate operations per second), up to 2,200 Mbps memory bandwidth, and size-reduced packaging. This represents a compelling price/performance breakthrough that hits the mark for applications such as digital front-end (DFE) and baseband solutions in a single-channel picocell wireless base station; military mobile software-defined radios (SDRs); ultrasound systems; driver assistance/media systems; high-definition video; and Smart IP cameras.

Moreover, with as much as 53,712 logic cells, 2,268 Kb of block RAM, 373 Kb of distributed RAM, 519 I/O pins, DeviceDNA for security, and newly developed hibernate/suspend power-management features, Spartan-3A DSP offers enough integration capacity to drive price/performance/power ratios even lower. Add to this the inherent benefits afforded by FPGA-based DSP solutions – lower risk through design flexibility and faster time to market – and the value of the Spartan-DSP platform becomes increasingly apparent (see Table 1). [more]

The next few years will bring great changes in the way our society views the high-tech community. We're in the early stages of a transition that will result in recognition of the electronics industry as a major contributor to the resolution of the world's global warming problems. To date, companies are talking about power reduction initiatives, but more can be done. From the design of "power-smart" chips and systems to the development of industry-wide power efficiency guidelines, the new power paradigm calls for the electronics industry to take responsibility for reducing energy consumption, improving power efficiency and ultimately, reducing greenhouse gasses.

"Power" in a Changing World
In the 1990s, "power" was discussed in relation to supplying power to a system or providing volts and amps to a PC card. And, for most people, "low power" was about a few power-conscious products that looked good on paper, but often saw little success.

Power in semiconductor devices takes two basic forms: static and dynamic. Static power is consumed when the part is not doing any useful work, while dynamic power is consumed when the device is actively working. Until recently, dynamic power was the dominant source of power consumption. Once helping to manage the dynamic power problem, device supply voltages (VCC) had scaled downward with process shrinks and subsequent lower system voltages, but the days of continued scaling are gone. Additionally, the physics associated with integrated circuits (ICs) on smaller process geometries have dramatically increased power related to leakage. And, with leakage worsening, static power has begun to dominate the power consumption equation as the biggest concern (Figure 1). [more]

The use of Digital Signal Processing (DSP) in electronic products is increasing at a phenomenal rate. Field-Programmable Gate Arrays (FPGAs), with their multi-million equivalent gate counts and DSP-centric features can offer dramatic performance increases over standard DSP chips. They also offer an attractive alternative for small and medium volume production. FPGAs also make very powerful prototyping and verification vehicles for real-time emulation of DSP algorithms [1].

This paper discusses the challenges and requirements of creating portable algorithmic IP for FPGAs and ASICs and illustrates how an ESL synthesis methodology using Synplicity’s Synplify® DSP tool can significantly reduce the time and effort to implement either technology. The Synplify DSP tool automatically creates optimized logic implementations for both FPGAs and ASICs.

Challenges in Porting RTL between FPGA and ASICs
The design team might ask: why is porting RTL between FPGAs and ASICs a problem? After all, isn’t RTL (synthesizable Verilog and VHDL) supposed to make the design portable? The answer can be quite lengthy and varies depending on the type of design. But for DSP algorithms, a general answer is that the RTL often specifies the exact mapping of key operations like multipliers, adders, and storage. Another way of saying this is that although the RTL is portable at the logic level, it is not at the architectural level. If synthesized to a different target, the same RTL will yield less than ideal results; in a different target technology, the result may be functionally correct but very sub-optimal. [more]

In complex signal-processing designs, designers must weigh the tradeoffs between the programming flexibility of discrete DSPs and the performance flexibility available in dedicated hardware while considering the needs of their system. The effort of creating DSP hardware was a major deterrent for all but the most performance-hungry applications. However, a new design methodology called algorithmic synthesis makes is easier to create high-performance dedicated DSP hardware. With this methodology, designers can automatically create RTL implementations in seconds, compare multiple micro-architectural options, and quickly achieve designs that are optimized for the application at hand. With these capabilities designers find themselves seriously rethinking their overall design flow when implementing algorithms in hardware, via either ASIC or FPGA.

Processing performance required for next-generation compute-intensive applications, such as wireless communication and image processing, has created a gap between off-the-shelf DSP performance and market needs. More and more, discrete DSP devices fall short of performance requirements for leading-edge communications and multimedia applications. In recent years, system designers have increasingly looked beyond programmable DSPs toward dedicated hardware solutions, such as FPGAs and ASICs that deliver increased levels of performance.

However, manually implementing DSP algorithms in hardware can be an expensive, time-consuming process. Hand-coding hardware descriptions in RTL can take a design team weeks or months, with verification and optimization doubling or even tripling the total time required to implement complex DSP algorithms. This effort and expense meant that ASICs and FPGAs were only used in demanding niche applications. Now, new algorithmic synthesis design tools, such as Catapult® C Synthesis, make it faster and easier to implement DSP algorithms in hardware, and put within easy reach hardware implementations that are optimized for performance, area or power consumption. [more]

Emerging broadband wireless protocols, based on WiMax and its derivatives, demand an increasing amount of throughput and data-rate. Fast chip-rate and digital RF processing by these protocols are optimally implemented in hardware using FPGA solutions.

FPGAs are ideal as a high-performance, cost-effective solution to implementing the digital functionality of these physical layer protocols because they include the following resources:

• DSP blocks to implement the multiplier and adder/accumulator functions required for various FIR filtering and FFT/IFFT operations.
• SERDES transceivers to support CPRI and OBSAI interfaces between radio heads and baseband digital boards
• Significant FPGA embedded block memory (EBR) to store filter coefficients, perform block interleaving and implement FEC decoding (Turbo, Viterbi, Reed-Solomon, etc.)
• High-speed LVDS I/Os to support wide parallel interfaces to and from D/A and A/D converters, respectively. Converters define the boundary between RF / analog functions and less expensive digital baseband logic. Higher rates of this interface allow more integration of digital upconversion / digital downconversion functions into the low cost FPGA solution.

This article focuses on the first resource, DSP multiplier blocks. Through reduction and optimal implementation of DSP multiplier blocks in FFT and FIR implementation, the designer is able to minimize resources while meeting throughput requirements. This allows users to migrate to the most cost-effective FPGA devices available. The four reduction techniques are as follows:
[more]