I/O Assignment is a Daunting Challenge
As more and more designers adopt FPGA devices with higher pin counts, the process of defining the I/O pin configuration or “pinout” has become a daunting task. The challenge is to balance the requirements from both the FPGA and PCB perspectives while designing both sides in parallel. Performing early I/O pin planning helps avoid having to iterate the pinout much later in the design cycle. Prematurely optimizing a pinout specifically for the PCB or FPGA often leads to design issues in the other domain. Pinouts defined to minimize routing concerns or layers on the PCB often lead to sub-optimal FGPA implementation. Pinouts optimized for the FPGA layout often cause PCB routing difficulties. Designers need to be able to visualize both the PCB placement and FPGA physical device pins along with the internal FGPA I/O pads and related resources to understand the ramifications of their pin assignment choices (Figure 1).

Assignment choices are typically made based on the PCB component interfaces. Critical signals and buses need to be assigned to pins on the same outside edge as the component to which they interface while maintaining “clean” routing of the signals. Especially in the case of large ball grid array packages, it can be very difficult to define the I/O pins to enable all of the PCB routing to exit cleanly. Depending on the PCB technology used, routing to the internal pins of these ball grid array (BGA) devices can be difficult or even impossible at times. Utilizing the outer pins of the device can make routing easier and wire lengths shorter. An optimal pinout can often reduce the PCB layer count or the number of PCB vias required to route all signals out from the FPGA package (Figure 2). [MORE]

Introduction
The embedded market continues to move toward 32-bit processing. At the same time, the market has seen a significant increase in the use of FPGAs as flexible, cost-effective platforms for the rapid design of high-performance embedded systems. In combination, these trends are driving demand for 32-bit processors in programmable logic.

Certainly, there is no end to the number of new 32-bit processor architectures. However, most processor intellectual property (IP) is developed for ASIC implementation. As a result, when implemented in the coarse-grained architecture of FPGAs, the processors are often large and slow—a fate suffered by many widely used processors when ported to programmable logic. Of course, a few soft proprietary IP processor solutions are available for FPGA implementation. However, only limited tools, support, and designer experience exist for these proprietary solutions, making them harder and riskier to use.

What has been lacking in the market is an FPGA-optimized, 32-bit processor based on an industry-standard architecture. To address this need, Actel and ARM® developed the 32-bit Cortex-M1 processor (Figure 1), the first ARM core designed specifically for FPGA implementation. [MORE]

Introduction
Timing-closure is a growing concern for FPGA designers, particularly with the recent introduction of multi-million gate architectures fabricated at the 90nm and 65nm technology nodes. It is not sufficient for a timing-closure solution – the entire flow, including synthesis – to only meet the required timing; such a solution must also minimize the number of time-consuming synthesis-place-route iterations and provide results that remain stable across multiple physical synthesis runs and during final routing.

A Problem With Conventional Technologies
It is no secret that wire delays dominate cell delays in modern silicon chips. In the case of FPGAs implemented at the 90nm technology node, for example, wire delays can account for 80-to-90% of each delay path. This causes a problem with conventional FPGA synthesis solutions, because only the cell delays are known, while the wire delays – which cannot be fully characterized until after place-and-route – are estimated.

As noted in Figure 1 below, the distribution of delays – the difference between what is estimated after logic synthesis compared to the actual delays following place-and-route – increases with each technology node and also as a function of the size of a design. [MORE]

In recent years, FPGAs have tremendously evolved in terms of capacity and performance. They’ve taken on more core functionality of a system. Therefore logic and constraint content of the FPGA place and route (P&R) tool inputs have increased. From an algorithmic perspective, extra features and density often represent an exponential complexity. If left unchecked, implications of this complexity on place and route runtime could become quite an impediment to designer’s productivity. At the same time, from a user perspective software runtime must be kept reasonably “fast”. Today, whether it is during logic creation, logic verification, design constraints closure or in-system debugging, designers need the ability to perform multiple design iterations through the place and route tool per day in order to move the project toward completion at an acceptable pace to management.

The first section in this document places the FPGA design cycle in the broader context of the entire system development. It highlights which steps typically require fast implementation runtime and for each step what the design properties are. The second section covers ISE 9.1i algorithm improvements and a description of new flows and options available to control software runtime. In the last section we list a set of common project and design strategies which affect runtime. [MORE]

Introduction
The field programmable gate array (FPGA) market has changed significantly in the past few years. Advances in silicon process technologies continue to augment both FPGA density and speed. As a result, an increased number of high-performance commercial applications, typically targeted at ASICs or ASSPs, now can be successfully, efficiently, and economically implemented in FPGAs. To achieve target performance, FPGA design engineers have adopted new clocking requirements (via clock multiplexing design schemes) and implemented design interfaces (such as source-synchronous clocks) that are difficult to analyze using traditional FPGA timing analysis.

This paper describes the new requirements that FPGA design software must satisfy to quickly and efficiently perform timing analysis and achieve timing closure. (For the purpose of this paper, timing analysis and static timing analysis are the same tasks performed with the same static tools. For brevity’s sake, we will refer simply to timing analysis.) Productivity requirements include the adoption of an industry-standard timing analysis methodology, and this white paper will illustrate a few practical applications of the industry-standard Synopsys Design Constraints (SDC) format. Additionally, productivity is enhanced by integrating the timing analysis engine with the place-and-route engine. Altera has used these requirements to develop and implement Quartus® II TimeQuest timing analyzer, a new, ASIC-strength static timing analysis tool with native SDC support. This paper will conclude with a short description of the timing analyzer's main features. [MORE]

Introduction
Traditionally, digital logic has not consumed significant static power, but this has changed with very small process nodes. Leakage current in digital logic is now the primary challenge for FPGAs as process geometries decrease. While the move to the 65-nm process delivers the expected Moore's law benefits of increased density and performance, the performance increases can result in significant increases in power consumption, introducing the risk of consuming unacceptable amounts of power.

If no power-reduction strategies are employed, power consumption becomes a critical issue because static power can increase dramatically with the 65-nm process. Static power consumption rises largely because of increases in various sources of leakage current. Figure 1 shows how these sources of leakage current (shown in blue) increase as the technology makes smaller gate lengths possible (shown in green). In addition, without any specific power optimization effort, dynamic power consumption can increase due to the increased logic capacity and higher switching frequencies that are attainable.

Power consumption is composed of static and dynamic power. Static power is the power consumed by the FPGA when it is programmed with a Programmer Object File (.pof) but no clocks are operating. Both digital and analog logic consume static power. In an analog system, static power is primarily composed of the quiescent current of the analog circuit based on its interface configuration. The sources of static leakage current in 65-nm are shown in Figure 2 and Table 1. [MORE]

Traditionally FPGA designers have been concerned with timing and area efficiency however as FPGAs have moved more and more into a role of replacing ASSPs and ASICs they have been pressured to develop lower power designs, produce better power estimates earlier in the design flow, and manage and sequence a variety of core and I/O voltages that often accompany FPGA implementations. Management of power has become an important consideration for FPGA designers especially those that target portable, battery-powered products. Using power-aware design techniques can help reduce consumption, increase the reliability, and lower cost of production with leaner power supplies and fewer cooling requirements.

Here are some key problems you might face with any FPGA power implementation: What will be the system-level power supply requirements? What will be the current draw? What voltage levels will be required and what power-up/down issues are there? What will be the thermal conditions of the device and will it work reliably given the environment and design I expect to run? Will I need to design in cooling mechanics to the board to counteract a hot part?

Power Theory
Power in electronic devices is often defined as the amount of work done by an electric current. Devices tend to convert work into heat, which unfortunately is not considered very useful in most applications unless your design is a heater or a light bulb! Understanding FPGA thermodynamics will help you identify the high-impact, low-effort methods to reduce power. Total power is a function of certain types of sub-power producers along with the characteristics of the process node and device packaging. [MORE]