CURRENT FEATURE ARTICLES

Auld Langxiety
Bracing for 2008
New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support
by Daniel Platzker and Jaggi Balasubramanian, Mentor Graphics
Zeroing in on Power
Altera Announces Max IIZ
Using CPLDs to Replace or Augment Microcontrollers
by James Adams, Altera Corporation
Legacy of Languages
Culture in Code
Altium Goes 3D
Board Design can be Fun

JOURNAL WEBCASTS

Xilinx Virtex-5 Power Optimization & Power Design Guidelines (Xilinx)

Virtex-5 FPGAs and PlanAhead Deliver Maximum Performance (Xilinx)

Accelerate Delivery of Built-in Ethernet Solutions Using ilinx FPGAs and Gigabit Ethernet Development Kit (Xilinx)

Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA (Xilinx)

Discover How the Complete Virtex-5 PCI Express Solution Reduces Risks for Your Application (Xilinx)

An Introduction to the Xilinx Virtex-5 FPGA Family (Xilinx)

Addressing Size, Weight, and Power Constraints (Altera)

Enable High-Volume Applications with New Low-Cost FPGAs (Altera)

Implement PCIe, GbE & SRIO with Altera's Low-Cost FPGAs (Altera)

CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

CHALK TALK Did you miss the ARM Developers' Conference?  Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Auld Langxiety
Bracing for 2008

Bonnnngggg…

Two thousand and seven creeps quietly toward a dignified death, trailing tales of victory and woe in the vast vortex of its widening wake.

Bonnnngggg…

Two thousand and eight eases expectantly into view, its perils and possibilities awaiting their unwitting victims and victors with equal voracity.

Bonnnngggg…

Mister Moore is a maddening mistress.

Naught seven was a year of hunker down and deliver.  In terms of new product announcements in the FPGA sphere, it was a year of bolster and boost, respond and reinforce.  Since it was an odd-numbered year, we didn’t have major Moore’s Law announcements – you know, the ones where the FPGA companies say “Announcing the new XYZ-nanometer Razmatazz FPGAs – Faster, Cheaper, and with Lower Power than anything ever produced, with new Secret Sauce features that we hope our competitors don’t have when they launch their XYZ-based devices” and with fine print that tells you we’re just kidding for this year, and you can expect volume shipments of this family in a year or more after we’ve figured out how to actually build the things. [more]

New Approach to FPGA Physical Synthesis for Ease-of-Use and Wide Device Support
by Daniel Platzker and Jaggi Balasubramanian, Mentor Graphics

In the past, physical synthesis tools for FPGA design were targeted to the advanced user and provided support for only a limited subset of devices. This has largely restricted the wide adoption of the technology. As a result, the Electronic Design Automation (EDA) tools have been inadequate in supporting the performance capabilities of the FPGA fabric. This article will examine the currently available FPGA physical synthesis tools and how a new generation of physical synthesis technology can help achieve timing closure faster, easier, and for a wider range of FPGA devices. [more]