CURRENT FEATURE ARTICLES

Legacy of Languages
Culture in Code
Altium Goes 3D
Board Design can be Fun
Improving ADC Results Through Oversampling and Post-Processing of Data
by Jim Vorgert, Actel Corporation
Designing Down Power
Actel Boosts Low-power Tool Suite
Physical Synthesis Flows for FPGA Designs
by Frédéric Rivoallon, Xilinx, Inc.
MicroBlazing Away
Xilinx Boosts Embedded Ecosystem
FPGAs Control Graphics and Video in Embedded Systems
by Kerry Howell, Lattice Semiconductor Corporation

JOURNAL WEBCASTS

NEW Xilinx Virtex-5 Power Optimization & Power Design Guidelines (Xilinx)

NEW Virtex-5 FPGAs and PlanAhead Deliver Maximum Performance (Xilinx)

NEW Accelerate Delivery of Built-in Ethernet Solutions Using ilinx FPGAs and Gigabit Ethernet Development Kit (Xilinx)

NEW Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA (Xilinx)

NEW Discover How the Complete Virtex-5 PCI Express Solution Reduces Risks for Your Application (Xilinx)

NEW An Introduction to the Xilinx Virtex-5 FPGA Family (Xilinx)

Addressing Size, Weight, and Power Constraints (Altera)

Enable High-Volume Applications with New Low-Cost FPGAs (Altera)

Implement PCIe, GbE & SRIO with Altera's Low-Cost FPGAs (Altera)

CHALK TALK Advancing SoC Verification Methods – Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Real World Solutions for FPGAs in Ultra Low Power Applications - Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)

CHALK TALK Did you miss the ARM Developers' Conference?  Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Legacy of Languages
Culture in Code

Using VHDL or Verilog to design FPGAs is just plain wrong.

Talk with any expert in languages, in logic synthesis, in hardware architecture.  If you get past the “but that’s how we do it” layer of defenses, you’ll pretty quickly uncover a vast ocean of oddity that will make you wonder just why anyone ever considered the idea of doing FPGA design with HDLs, let alone how HDL-based design became the de-facto standard.

First, taking VHDL as an example: most of the things you can write in VHDL cannot be synthesized into hardware with any degree of efficiency.  In fact, to paraphrase one of my favorite college math professors, if you wrote all the possible VHDL on a big wall, and threw tomatoes at the wall all day long, you’d probably never hit any code that would synthesize well.  (This is a variant of what my professor called the “tomato theorem.”)  Those of us that successfully write VHDL for synthesis have learned through experience how to step on a select few hidden rocks just under the water’s surface in order to keep our footing through synthesis.   Deviate from those rocks, however, and you’re likely to take a dunk in code that won’t synthesize at all or will create hardware that’s impractically inefficient if not completely un-buildable.

Of course, VHDL wasn’t intended for designing hardware.  Yes, the D stands for “Description,” but in its original context, that “Description” was more like “Documentation.”  VHDL was intended to solve a documentation problem for the US Department of Defense.  The advent of application-specific chips had created a daunting documentation problem for both the DoD and its suppliers, and VHDL was developed to address that challenge.  Now, ASIC designs could be described in a standard, machine-readable language instead of through piles of ad-hoc paper documentation. [more]