FROM
THE EDITOR
This week, we take a look at the new low-power development tools being released with Actel’s latest Libero suite. With new super-stingy low power FPGAs on the market, design tools that help us maximize their value are a critical next step. Our latest feature has the details.
Also new this week, we have a contributed article from Frederic Rivoallon of Xilinx about physical synthesis for FPGA design. Physical synthesis can make significant improvements in the timing performance of your design, and can also dramatically reduce the number of iterations required to meet timing.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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Designing Down Power
Actel Boosts Low-power Tool Suite
Now that it is officially OK to use FPGAs in battery-powered devices, we’re seeing two groups of designers converging on the low-power FPGA design topic. First, there are those who have been working on low-power and portable applications for years and are just now taking on FPGAs for the first time. Second, there are those who have been doing FPGAs for years, but have never needed to perform power-conscious design because their FPGA designs were always run from small dedicated nuclear power facilities. While both of these groups are learning new techniques, the thing they have in common is the need for low-power FPGA design tools.
Actel has just released a new version of their Libero development tools (version 8.1), and the focus is all on improving low-power design. It makes good sense. Actel currently has the champion among low-power FPGAs (if you’re judging based on power consumption) with their Igloo family. [more]
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Physical Synthesis Flows for FPGA Designs
by Frédéric Rivoallon, Xilinx, Inc.
Most FPGA designs today rely on an HDL based description of their design. HDL synthesis is probably the single most important software flow step when it comes to defining the performance of a design. Synthesis links the conceptual description of the logic functions needed for the design to their actual physical architecture elements in the underlying device. This step cannot be underestimated. Synthesis is performed prior to chip placement as an entirely separate step, hence these technology dependent optimizations are computed without knowledge of actual chip placement. As a result, design performance can be far from optimal, impacted by choices made too early. This is where physical synthesis comes into play, bringing physical information to the synthesis engine.
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