FROM
THE EDITOR
Double check your PRMs, confirm the DRCs, check the wind one last time and jump! If you’ve done your design correctly, you’ll land safely at the bottom under a canopy of correct logic. Make a mistake and your FPGA will lock up in a jumble of mis-matched bitstreams and wrongly routed connections. Partial reconfiguration is FPGA design’s closest thing to BASE jumping. It’s a high-risk enterprise that demands exacting preparation. This week, we take a look at the latest in the extreme sport of partial reconfiguration for software-defined radio.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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FPGA BASE Jump
Partial Reconfiguration for SDR
Louis walked the last flight of stairs to the roof with his gear in tow. Sebastian followed him and helped check the rigging. Louis got his bearings on the edge of the roof while Sebastian checked the wind one last time. The tell-tale strand of yarn on the handheld wind meter streamed backward and up as the LCD read the velocity. The perfect time was… Now! Louis pushed off and smoothly transitioned into his freefall form while pulling the release for the parachute. As his body raced toward the terminal velocity of 55 meters per second, the canopy inflated above his head. A powerful SNAP jerked him upward and he immediately grabbed a line to steer himself to the left, avoiding the building across the street and heading him toward his landing zone.
Sebastian walked inside and took the elevator to the bottom, arriving at the street less than a minute after Louis landed.
Clearly Louis isn’t participating in the extreme sport of BASE jumping (an acronym for Buildings, Antennae, Spans, and Earth) just to get to the bottom of the building faster than Sebastian. While BASE jumpers would probably be elated if a practical application for their sport suddenly materialized, they are content with the thrill they get from planning and executing such an exacting, death-defying feat of engineering and athleticism.
Very little in electronics engineering even approaches the realm of death-defying. Career-limiting is probably as close as we typically get. If you’re designing a high-end ASIC and you’re trying to avoid being the one whose mistake causes a re-spin, you may have a lot in common with a BASE jumper – triple checking everything before the critical moment to be sure that all is in perfect order.
In FPGA design, the closest thing we have to an extreme sport is partial reconfiguration. It may sound easy – leaving your FPGA operating while only a portion of it is re-configured with a new bitstream -- but the reality of the situation is much more challenging. Partial reconfiguration is a bit like a surgeon trying to operate on himself while under partial anesthesia. It’s difficult to get the part you’re working on separated cleanly from the part that’s doing the work. [more]
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