FROM
THE EDITOR
This week, we drop in on DRC and take another overall look at the state of reconfigurable computing using FPGAs. A colleague of mine said “Reconfigurable Computing is the technology of the future… and always will be.” Perhaps his cynical prediction is coming to an end as taking advantage of reconfigurable computing technology continues to become easier and more cost-effective. Our latest feature takes a look.
Next, we have a contributed article from Navneet Rao of Xilinx who tells us about FPGAs and Ethernet. The flexibility of FPGAs with the ubiquity of Ethernet makes a powerful combination. Rao supplies the details in our second new article.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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COTS Supercomputing
DRC Harnesses FPGAs
COTS (Commercial Off-The-Shelf) is a term we’re accustomed to associating with government or military/aerospace technology. The basic idea is to reduce costs by using readily-available commercial technology wherever possible instead of creating new, purpose-built subsystems. In things like military applications, significant savings can be realized by intelligently substituting COTS technology where it can reasonably do the job.
The field of High Performance Computing (HPC) shares a similar situation. Because high-performance computers are built in very limited quantities, custom-designed subsystems add significantly to the cost of the overall system – even when they’re not in the performance-critical path. If we could build supercomputing systems with as many COTS components as possible, we would stand a chance of significantly cutting the cost of all those teraflops.
A couple of years ago, we talked about the potential of FPGAs as reconfigurable computing elements for specialized tasks in high-performance computing. HPC was perhaps the first industry to hit the processor power wall, switching from monolithic processors to large arrays of parallel processing elements. However, for many computing tasks – particularly those with looping constructs, much more power-efficient computation can be accomplished by implementing parts of the algorithm (or in some cases the entire algorithm) directly in hardware such as FPGAs. If you have, for example, an application that requires large numbers of multiply and accumulate operations that could be executed simultaneously, a properly configured high-end FPGA with hundreds of multipliers can outperform a traditional von Neumann architecture by orders of magnitude – both in speed and in computational power efficiency. [more]
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FPGAs and Ethernet
Providing Programmability to Pervasive Interconnect Standard, by Navneet Rao, Xilinx, Inc.
Ethernet is the most widely used connectivity technology today. Previously limited to WAN and LAN, Ethernet is now making inroads into industrial, medical, video, aerospace and defense markets. Ethernet can be used not just for the data path but also on the control plane for applications, such as system management, remote monitoring and debug. Ethernet usage is predicted to rise rapidly in the coming years (Figure-1: Escalating Ethernet Use). While Ethernet specification defines several speeds from 10 Mbps to 10 Gbps, the fastest growing segment is Gigabit Ethernet, mainly due to migration of desktop connectivity from 100 Mbps fast Ethernet. Embedded designs, however, will continue to use connections at 10/100 Mbps speeds. 10 Gbps Ethernet is typically restricted to high-end bandwidth applications, such as multi-gigabit serial backplanes and fat data pipes. [more]
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