a techfocus media publication :: June 12, 2007 :: volume XV, no. 10

FROM THE EDITOR

This week, we apply the principles of Cajun cookin’ to the problem of FPGA configuration.  Flour, Flash, oil, and just the right amount of heat and software and you’ve got yourself a solution that’ll bake your bitstreams to perfection.  Confused?  Our latest feature may help sort it all out.

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Kevin Morris – Editor
FPGA and Structured ASIC Journal


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CURRENT FEATURE ARTICLES

First, Make a Roux
Beyond Basic FPGA Configuration
FPGAs at DAC
Programmable Logic Powers Verification

Lattice Leaps Forward
90nm XP2 a Fit Sequel
FPGA Packaging and Signal Integrity
A Connectivity Perspective

Merging Lanes
Will FPGAs Re-converge?

Beyond the Go Button
Taking More Control of FPGA Design
Serial Commodotization
Altera Arria GX

It Isn’t Easy Being Green
Weee Review RoHS Basics

JOURNAL WEBCASTS


First, Make a Roux

Beyond Basic FPGA Configuration

If you own a Cajun cookbook, you may have noticed that virtually every recipe begins with this step.  If you can’t make a Roux, you can’t cook Cajun.  The recipe for Roux (if you can find one) is always fairly vague – “Put some flour and oil in a pot and heat until the color changes to brown.” How much flour?  How much oil? How much heat? What shade of brown?  All of these questions are, as we learned in engineering school, “left as an exercise for the student.”  Of course, if you make your Roux badly, you are creating a dish that is crippled from the start.  Caveat Cook.

Designing with FPGAs works a bit like that.  Here in the techno-editorial world, we simply state that you’ll need “some configuration logic” attached to your device before you go off enjoying whatever wonderful new feature we’re about to disclose in our article.  What kind of configuration logic?  You know – throw some flash and a JTAG thingy into a pot, maybe a CPLD or two, heat until it turns brown, and there ya’ go.  Now, let’s talk about those new 18X18 multipliers… [more]

EVENTS & ANNOUNCEMENTS

Designing High-Density FPGAs? Use Quartus II Software!
Altera's Quartus II software delivers the highest performance and productivity for high-density FPGA designs. Learn how the Quartus II software can help you meet performance goals and finish your high-density design faster.
Learn how the Quartus II software can help you meet formance goals and finish your high-density design faster.


Flexible I/O Meets the Xilinx® VirtexTM-5 FPGA
VMETRO’s PMC-FPGA05 PMC Modules combine high speed digital I/O with the power of the Virtex-5 FPGA. Front-end interface options include dual channel 105MSPS 14-bit ADC, CameraLink, dual channel 210MSPS 14-bit DAC, RS422/485, FPDP and FPDP II, LVDS and L-Band Receivers.
Click here to learn more about this marriage made in heaven.

Implement PCI-E, GigE & SRIO with new low-cost FPGAs
In just 15 minutes, learn about Altera's newest FPGAs with transceivers: the Arria GX family. With support for three protocols, Arria GX devices are a low-cost, proven coprocessing option for your next design.
View the free QuickCast on demand now!


Free Job Postings on Journaljobs.com
JournalJobs.com – the job board for FPGA Journal and Embedded Technology Journal is now re-launching with a host of new features and capabilities. In celebration of JournalJobs.com grand re-opening, we’re offering free job postings through July 31, 2007.  Go online, post a job, pay nothing, and watch for those qualified resumes to come knocking on your inbox.
Click here to post your job listing on Journal Jobs!


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