FROM
THE EDITOR
This week, Lattice Semiconductor continued their roll of new product announcements with the debut of Lattice XP2 – a 90nm sequel to the popular Lattice XP family. XP2 combines SRAM fabric with embedded flash for almost-instant reconfiguration creating a versatile platform with SRAM performance and non-volatile features. Our latest article has the details.
Also, we have a paper by Xilinx’s Navneet Rao on FPGA packaging and signal integrity. With the proliferation of high-speed serial interfaces hitting FPGAs, signal integrity (SI) is becoming an increasing concern. Solving SI issues goes beyond your board design, however, as the packaging design of the FPGA itself has a big impact on SI performance. Navneet explains design features of Virtex-5 aimed at addressing the problem.
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FPGA and Structured ASIC Journal
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Lattice Leaps Forward
90nm XP2 a Fit Sequel
Don’t be fooled by quarterly results.
Lattice Semiconductor has been on a new-product rampage for the past two years. Beginning with their alliance with foundry partner Fujitsu, the company has put up an impressive streak of successful new product introductions. From the company’s first low-cost FPGA, the “El Cheapo” Lattice EC, to the just-introduced XP2 90nm non-volatile family, Lattice seems to have gotten its engineering act together in a big way.
Why haven’t their financial results shown it yet? In the FPGA business, the time from winning a socket on a customer’s board to realizing revenue from volume shipments can be 18 months or more. Selling lots of development kits and samples doesn’t do much for the bottom line initially. What it does translate into, however, is good potential for the future.
The newest entry in their programmable logic portfolio, Lattice XP2, is a sequel to their highly successful non-volatile Lattice XP line. In addition to rolling the product up to the latest 90nm technology (and blazing some new trails implementing flash in 90nm), the company has loaded some attractive new features onto an already well-regarded device. The new device weighs in at about half the cost per LUT of its predecessor, offers double the density, and eeks out some additional performance in the process. They’ve also thrown in some user-flash memory capability and beefed up their Live Update field upgrade process. [more]
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FPGA Packaging and Signal Integrity
A Connectivity Perspective
by Navneet Rao,
Xilinx, Inc
High-speed system interconnects have a large impact on integrated circuit (IC) package design. High-speed connectivity requires fabrication of packages that are able to support very fast varying, broadband signals with good signal integrity (SI). Based on Moore’s law, on-chip clock frequency doubles every 18 months and the intrinsic delay of the gate decreases exponentially to a few picoseconds (ps). Increasing I/O counts add another element to this equation. Rent’s rule states that the number of I/O will double in the next ten years, which means that there will be a lot more signal pins in a smaller area. And, in turn, the smaller dimensions of chip packages make SI problems more acute when compared to PC board. Poor signal integrity means added costs, delayed product releases, and even lost revenues. The cost of ignoring signal integrity can easily reach millions of dollars, especially given how important time-to-market is in today’s marketplace.
Signal integrity challenges of Faster and Wider I/O
As system interconnect speeds increase, transition periods decrease and signals have faster and faster switching characteristics, namely, faster rise and fall rates in hundreds of picoseconds. Since most SI problems are directly related to dV/dt or source-drain current transition (dI/dt), faster rise times negatively impact SI effects such as reflection noise, crosstalk noise and power/ground switching noise. [more]
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