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Merging Lanes
Will FPGAs Re-converge?
For years, we had just “FPGAs.” We didn’t have today’s high-end, low-cost, value-based, platform-enabled, I/O optimized, low-power, DSP-enhanced, SerDes-enriched flavors. The very nature of FPGAs was to be generic. They were, after all, reprogrammable devices that could tackle any task assigned to them (provided, at the time, that task didn’t require more than about 30MHz performance or more than a few thousand look-up-tables or any memory or even the merest modicum of power efficiency.) In other words – glue logic.
From those humble beginnings, the floodgates opened. FPGAs got bigger and faster. This rocket ride on the Moore’s law missile left behind it a trail of smaller and slower FPGAs – which, of course, had every bit as much utility as when they were originally designed. These FPGAs were primarily used in applications like telecommunications infrastructure – at a time when that industry had an almost insatiable appetite for density and performance combined with seemingly unlimited price and power budgets.
As the telecom boom went bust, however, FPGA companies went looking for greener pastures, or even more pastures that were the same color green, or even just pretty much any pastures at all where people might possibly prefer programmable logic to lower-volume ASIC implementations. Of course, this meant that the architects of programmable logic devices had to start listening to a much more diverse audience of customers than ever before. Instead of just blindly chasing the technology curve with density and performance, they had to begin to make delicate tradeoffs among things like features, performance, cost, density, power, and pinout.
For different markets and applications, different things were important. In order to serve all those masters, FPGAs started packing on the pounds with additional features for just about every conceivable situation. Processor cores, memory, multipliers, complex clocks, a bevy of I/O standards – all led to big, costly, power-hungry Swiss-army knife devices that could do almost everything but weren’t particularly well suited to any particular task. Almost all at once, FPGA companies abandoned the one-size-fits-all strategy for broad portfolios of devices with varying mixes of capability. [more]
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