FROM
THE EDITOR
This week, we roll with the RoHS – examining the trends and terminology behind today’s new, greener electronics manufacturing standards. With Moore’s Law obsolescing a full generation of electronic products every two years, a lot of the stuff we work so hard to design quickly ends up in landfills. Here’s a quick primer on the standards that are helping us reduce the impact on the environment.
Many of us that only dabble in FPGA design depend on the freebie, web-based tools from the FPGA vendors. If you’re serious enough to want commercial EDA tools in your design flow, however – you’ll want to think about how that flow is integrated between the various tool components. Tom Dewey of Mentor Graphics gives us a rundown on the benefits of an integrated flow.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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EVENTS & ANNOUNCEMENTS
What makes Actel’s true Flash technology better than the rest? Actel’s Flash FPGAs offer a unique combination of nonvolatility and reprogrammability within a single-chip, providing an easy-to-use, secure, reliable, low-power, cost-effective solution. Although often imitated, the advantages of Actel’s True Flash FPGAs cannot be duplicated.
 Learn more.
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Free Job Postings on Journaljobs.com
JournalJobs.com – the job board for FPGA Journal and Embedded Technology Journal is now re-launching with a host of new features and capabilities. In celebration of JournalJobs.com grand re-opening, we’re offering free job postings through April 30, 2007. Go online, post a job, pay nothing, and watch for those qualified resumes to come knocking on your inbox.
 Click here to post your job listing on Journal Jobs!
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Free Seminar - Winning Webcasts
Does your company do webcasts? Want to make them better? FPGA Journal's Amelia Dalton will show you how in this free online seminar "Winning Webcasts".
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It Isn’t Easy Being Green
Weee Review RoHS Basics
We all know the basics of Moore’s law, right? Every new process node brings a bounty of the three “Ps” - Price, Performance and Power. Most of us can recite them like the alphabet. Missing from our recitation, however, might be some other things that come with a new process node – Lead, Mercury, Cadmium, Chromium, PBBs and PBDE – now THOSE will taste nice on your breakfast cereal. Electronic waste is a major polluter, and, thanks to Moore’s Law, we always have better, faster, cooler products to offer the public – inspiring them to take our last year’s products and dispose of them irresponsibly. As a result, in the US, electronic waste is estimated at two percent of the contents of landfills, and 70 percent of toxic waste.
Yes, I see your hands in the back again. (Why is it always the people in the back who raise their hands?) “Aren’t we all RoHS now? Isn’t this problem gone?” Well, the answer is that many of us are RoHS now, but our newer, greener, RoHS-er products are mainly the ones consumers are currently purchasing. Once they have these new, shiny, green devices, they’re taking their old lame lead-laced ones and tossing them into the environment. [more]
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The Value of a Complete
FPGA Design Flow
by Tom Dewey, Mentor Graphics
If the chain of tools comprising your design flow works flawlessly in getting your hardware ideas to silicon quickly, then the value of that flow is priceless. However, if one or more of the links in that chain is broken or corrupted, then the value of that flow plummets.. Whether you are thinking about assembling a new design flow or auditing your existing flow, this paper covers methods for improving the effectiveness of that chain of tools.
Introduction
Design flows tend to grow in complexity over time. These flows consist of commercial tools bound together with scripts, home-brewed tools, and free-ware to form a design environment. This flow works well until a new design breaks it. At this point, a mad frenzy of activity takes place to track down the fault and fix the problem. In examining a design flow that has evolved over time, it is difficult to understand all its elements. This seamless flow, in fact, tends to be held together with a lot of script putty that grows old and cracks with age. This breakage is likely to occur when a company shifts to modern design methodologies such as advanced verification or new languages such as SystemC and SystemVerilog. [more] |
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