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Sampling Some FPGA IP
Samplify Compresses Data and Design Cycles
FPGAs are a series of pipes. They’re not something you just dump something on. They’re not a big truck. If you don’t understand that, those pipes can be filled, and if they are filled, when you put your data in, it gets in line and it’s going to be delayed by anyone that puts into that pipe enormous amounts of material, enormous amounts of material.
Apologies to US Senator Ted Stevens (R-Alaska)
OK, maybe that’s just plain mean, but many people use FPGAs as big pipes. You have an enormous amount of material coming in from, say, a high speed sensor, and you need to somehow manage the flow of that data into the rest of your system. FPGAs are the undisputed connectivity masters in such situations. Frequently, designers will plop an FPGA between the sensor and the rest of the system. The FPGA may be doing some down-conversion or some high-speed parallel DSP processing near the point of origin. It may be also taking advantage of high-bandwidth I/O to distribute the incoming data to multiple channels where it can be processed at a more leisurely and reasonable pace.
One of the most efficient things you can do with that data is to compress it as close to the source as possible. Then, your “series of pipes” can be much smaller throughout the rest of your system, as you’ll be dealing with compressed data instead of raw data. Wouldn’t it be nice if that compression could be done right there in your FPGA (since you’ll be using one anyway)? [more] |
