The First FPGAs of Spring
An Ode to Progress

The wild winds of winter have ravaged the technology plains with bitter cold, their icy breath wearing thin the layer of protective press releases lovingly laid down to protect the crops during the dormant days of digital design.   Groggy-headed marketers return from Maui and the extra-worldly environment of their sales kickoff events to face the bleak reality of product releases awaiting their magic touch.  The frozen pond of high-tech public relations may look barren today, but a barrage of activity blossoms just beneath the surface.  The technology universe, too, is tilted on its axis, and the inevitable swing of the seasons will bring the bounty of Moore’s Law to all the land.

The silence of the still-frozen water is barely broken by stealthy whispers of embargoed news releases – audible to only a few.  Beneath the surface, however, the dance of the datasheets has begun.  Early access customers fiddle with fledgling technology, hoping to gain some modicum of technical advantage – and in return, sell their professional souls to quotecrafters who will express opinions they haven’t yet formed with far greater eloquence than they themselves will ever possess. [more]

Deterministic Name Generation for Incremental Synthesis
by Quan Dinh Tran and Dan Devries, Mentor Graphics Corporation

Introduction
Incremental design is a useful capability when implemented properly. Unfortunately, due to the naming schemes employed by logic synthesis tools, confusion arises over what in the design has actually changed. What is needed is an algorithm that deterministically creates names for generated logic elements, simplifying the task of correctly identifying what has changed at each cycle.

For the incremental design flow illustrated in Figure 1 to be most effective, minor changes should be made to the design at each incremental turn to allow the reuse of the place-and-route data generated during the previous design turn. The major benefit of this methodology is the generation of a predictable design output similar to the previous place-and-route run, plus the associated shortening of the runtime. [more]