DSP to a Different Drummer
Stretch Debuts S6

FPGAs, possibly the most powerful processors in existence today by many measures, were never intended to be processors at all. Conceived as general-purpose programmable logic devices, their simple arrays of logic elements were not designed to accelerate computationally intensive tasks. Instead, they fell into the role in a Rube-Goldbergian fashion – evolving their processing prowess over a decade or more with engineering’s version of emergent behavior rather than ground-up purposeful design.

Today, FPGAs are used in many applications for heavy lifting chores such as video processing, often paired with conventional processors charged with handling the housekeeping. While the hardware is clearly capable, the ad-hoc programming model is anything but straightforward. Typically, FPGAs achieve “accelerator” status only after the algorithm goes through a bizarre set of transformations from some high-level description to a bit-true, cycle-accurate representation, then to register-transfer-level descriptions, then through logic synthesis to a netlist and finally to a bitstream after place-and-route and mapping. Does this seem convoluted yet?

Several companies have been founded in the past several years on the proposition that there’s got to be an easier way. Surely we could design something from the ground up to accelerate computationally intense algorithms, avoiding the inherent complexities of FPGA design, while maintaining the performance and power benefits of highly parallel processor architectures. [more]