FROM
THE EDITOR
Last week, we looked at ChipX’s new embedded array platform, discussing how embedded arrays are a step between structured ASIC and full standard cell ASIC. This week, ChipX has acquired the US ASIC business unit of Oki, effectively doubling the size of the company and dramatically broadening the range of ASIC, embedded array, and structured ASIC they can offer. Our latest feature article takes a look.
Next up, we have a new contributed article from Bruce Riggins of Mentor Graphics. Bruce explains the issues and consequences of IO pin assignment in FPGAs when you get down to the board design level. Pin assignment can have a dramatic impact on timing, routing completion, and signal integrity in board design. Bruce also describes a design approach that can help mitigate the problems.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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Re-structured ASIC
ChipX Takes Oki’s US ASIC
Acquisitions are boring.
We all think so. That’s why we went into engineering.
So why should we talk about ChipX grabbing Oki’s US ASIC business? Is it the unusual “Private US company acquiring part of a Japanese technology giant” aspect? Is it the enigmatic cloud surrounding privately held semiconductor companies in general? Is it seeing a company that’s bullish on ASIC technology when worldwide ASIC starts are lagging? Did you notice that we used the word “bullish”? You can tell we’re in financial land now.
For those of us that dally more in clock skew than acquisition terms, here are the highlights of the deal (closed-captioned for technology professionals). [more]
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FPGA I/O Design is (also) a PCB Problem
by Bruce Riggins, Mentor Graphics Corporation
In FPGA-based systems, the traditional approach is to split the design at the boundary of the FPGA’s pins. Everything from the pins in is the responsibility of the FPGA designer while that outside the FPGA is handled by, well, everyone else. Which begs the question: who handles the pins themselves, that nebulous boundary that is part of the FPGA but whose assignments can have such a drastic effect on the quality of not the FPGA, but the PCB itself? Again, tradition holds that the FPGA designer does the I/O assignment - an often monotonous, tedious, but nevertheless essential, part of the process which offers little in the way of creative problem solving, at least from the FPGA designer’s perspective. Tools have evolved to ease the pain, but it is still the FPGA designer who is made to suffer through it. [more]
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