Un-structured ASIC
ChipX Announces Embedded Arrays

In the continuum of custom logic device technologies reaching from highly-custom Standard Cell ASIC at the high end to FPGA at the low end, we seldom hear from the node called “Embedded Arrays.”  The extremes get lots of publicity.  There is ample press and activity focused on both ASIC and FPGA, as these technologies are fairly easy to understand, and their benefits, problems, and trade-offs are quite familiar.  The middle is a little fuzzier and (usually unjustifiably) frightens away analysts, press, and even development teams. 

The “structured ASIC” flavor took a PR beating last year with LSI Logic’s rather visible retreat – cancelling their RapidChip product line.  The move prompted other supporting vendors (such as Synplicity) to retreat from the technology as well.  The combination of those events subsequently caused the press and analyst community to call the very idea of structured ASICs into question.

Structured ASICs have not gone away, however, with companies like ChipX, Altera, and others making a strong business from the technology.  There is still a strong need in the market to fill the technology gap between FPGAs and ASICs with a noble compromise – something that fits in between the two extremes with higher density, higher performance, and lower power consumption than FPGAs can offer – combined with more flexibility, easier design, lower non-recurring engineering (NRE) and faster time-to-market than standard cell ASICs.

ChipX has just announced what they call “Embedded Arrays,” which are arguably a new step in-between traditional standard cell ASIC and structured ASICs.  Embedded Arrays still use standard cell blocks for the performance-, power-, and area-critical parts of the design but have a gate array-like (sorry for using the now-forbidden “g” word) structure for custom logic and for easily creating variants on a basic platform. [more]