ISE Storm
Xilinx 9.1i Packs New Capabilities

For system designers, Moore’s Law is a gravy train.  Every couple of years, you get more gates, more speed, less power consumption, and lower cost.  For digital designers and tool developers, however, that gravy train is headed through the tunnel right at you.  Every couple of years, you have more gates to design in less time, more complexity to overcome, and tougher verification problems.  Your design tools are heavily impacted, too.  The old synthesis and place-and-route runs that took a few minutes on an old 200MHz Windows 98 laptop are now running for 24 hours on the latest multi-core, memory-laden, tricked-out machines. 

Xilinx’s latest software release goes straight at that problem, acknowledging that in this day of platform-based design, IP re-use, hardware/software verification, and high-speed serial I/O, the toughest FPGA design challenge for most people is still basic timing closure from RTL to bitstream.  Xilinx’s new ISE 9.1i includes two major enhancements: “SmartCompile,” to address timing closure on large designs, and some new power optimization capabilities to address the growing sensitivity to power consumption in today’s more FPGA-centric systems.

Xilinx tackled the runtime and productivity issue both in evolutionary progress on runtimes and algorithm efficiency (boosted by faster computing platforms, of course) and in more revolutionary change in the form of incremental design capability. 
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