After achieving an industry milestone, what's next? In 2005, the Xilinx® Platform Studio tool suite (XPS) included in the Embedded Development Kit (EDK) won the IEC's DesignVision Award for innovation in embedded design. The revolutionary approach of design wizards brought abstraction and automation to an otherwise manual and error-prone development process for embedded system creation.

The year 2006 brings a new version 8.1 update to the Platform Studio tool suite, with an emphasis on simplifying the development process and providing a more visible environment. The result is a shortened learning curve for new users and an even more complete and easier-to-use environment for existing designers.

Just getting a complex design started can take a significant amount of time out of a critical schedule, so Xilinx started with a premise that the first steps to a working core design should be automated. The Xilinx Base System Builder design wizard within the Platform Studio tool suite provides a step-by-step interface to walk you through the critical first stages of a design. Design wizards are a great innovation because they can provide a quick path to a working core design even if you have minimal expertise. The "smarter" the install wizard is, the fewer issues occur, and the less experience you need to have. [more]

Introduction
Altera has developed a configurable 32-bit soft processor core, called Nios ®II that has been designed for implementation in FPGA. Many features of the processor core can be configured to allow developers to trade off processor size and performance to match their application requirements. To enhance productivity the processor configuration is done using tool called SOPC builder. This tool also allows the developer to select and integrate processor peripherals from a library of components supplied by Altera, a third party IP provider or IP modules that the developer has integrated into the SOPC builder library. The properties of these components, including where they reside in the processor memory map and the interrupt used, can be easily changed using the SOPC Builder graphical user interface (GUI). As the tool is GUI driven it is very easy and quick to generate custom processor based systems. Once built systems can be edited at any time using the same graphical interface, making it easy for the hardware developer to modify and adapt the system until the required target for performance, size and features are met.

In order to accelerate the development process many developers choose to begin software development as early as possible. With a fixed processor the software environment is rigidly defined and the software engineer can plan and implement large parts of the code before the hardware is ready. [more]

Processing power has always been on every designer's mind, but today's market requires that designers also pay attention to power consumption. In this increasingly portable world, finding ways to extend battery life is no longer a consideration; it is a necessity. For FPGA users, power consumption can become an issue without mindful technology choices.

Designers usually do not associate low power with FPGAs because most FPGA types are SRAM and flash-based, using memory-controlled switch transistors to create the FPGA's programmable interconnections. These memory circuit structures draw power simply to maintain the interconnect programming, giving the FPGA a relatively high power consumption even when idle. In addition, while the latest generations of semiconductor process geometry have pushed memory-based programmable logic performance to its edge the processes have also caused major problems in terms of power consumption due to increased leakage current.

Designers may not be aware, however, of an alternative programming technology, the anti-fuse, that does offer low power operation. Anti-fuses, such as QuickLogic's ViaLink®, are an extremely fast, low power, non-volatile interconnect that eliminates the need for memory-controlled switches. The ViaLink anti-fuse element, for instance, consists of a high resistance layer (>1 GigaOhm) of amorphous silicon above a tungsten plug (ViaLink) that would otherwise bridge the insulation between two metal layers, as shown in Figure 1. [more]

When designing a packet processing subsystem, engineers have as a primary goal to make sure that the design can process packets as quickly as they come in. At gigabit line rates, this is no small task. Designing systems that process packets is straightforward; design them to do it quickly is where the magic lies. The biggest bottleneck in the rush to market is the time required to ensure that the design achieves line rate performance.

Gigabit-class packet processing is implemented on a variety of multi-core hardware platforms. Some, like the Intel IXP network processor family, consist of specialized processors in a tailored architecture. Others, like the Broadcom SiByte family, are multiple symmetric RISC processors that can be used to accelerate the packet processing load. Programming this kind of system can be a significant amount of work, and historically can involve a lot of low-level programming and tuning. Teja Technologies has eased this effort significantly by providing access to applications and tools that raise the level of programming to C, and which automate many of the more tedious tasks associated with managing multi-core processing without compromising performance. [more]

Each time a new SoC project starts, engineering managers are under pressure not only to develop the product on time but also way ahead of any competition. One of the key elements that decide about the speed of product development is the set of tools available to developers. Thanks to those tools many manual and time consuming operations for both development and verification can be speeded up, enhancing at the same time the product quality and other parameters. Another important factor is the methodology used for design development and testing. The main challenge on any SoC project is harmonious and effective cooperation between the hardware designers and software developers. The situation may be strenuous if software developers using ISS and software models need to wait for operational hardware, which wastes time and money. The biggest challenge for the team manager is always how to increase the team's productivity and minimize any idle time.[more]