FROM
THE EDITOR
This week, in our final issue of 2006, we take a look back at the year in programmable logic. After all, doesn’t every special interest field need one of these – like: “The year in inline skating”, or “Lederhosen 2006”, or maybe “2006 – A Big Year for Farm Implements”. In our annual wrap-up, we look at the major announcements from the major players, and also at how life has and hasn’t changed for those us in the FPGA world at large.
Our second new article comes from Anil Khanna and Shawn McCloud of Mentor Graphics’s high-level synthesis group. Anil and Shawn give us a look at the power of performing power optimization by exploring architectural alternatives. By viewing power and making architectural-level changes at a higher level of abstraction, you can have an enormous impact on the final power efficiency of many designs. This article gives insight into the practical aspects of high-level power-efficient design.
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Kevin Morris – Editor
FPGA and Structured ASIC Journal
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Dangling Propositions
2006 in FPGA
Every year, we put on our historian hats and look back at the events of the previous twelve months. (It turns out that our historian hats are orders of magnitude more accurate than our future-predicting goggles, by the way.) This year, the industry continued an inertial growth trend in both the technology and business axes. OK, there. We’re done. You can stop reading and head off to celebrate whatever holiday your particular culture observes this time of year -- even if it’s just international “the office is closed for a couple of days” day.
Still reading? Or – at least using this window to cover up the Amazon.com browser window behind until that oh-so-nosey person stops looking over your shoulder? They just won’t leave, will they? Little do they know that even the power of expedited shipping may not be able to help you now. Still, you can compare features online and then rush out to the local store for the final purchase. HINT: Beware pre-mature features. They may sound great on the data sheet, but when you get them home, you’ll see that there are serious obstacles to their practical deployment in your environment. Got any working 802.16 devices in your life yet? [more]
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Power Exploration in High-Level Synthesis
by Anil Khanna and
Shawn McCloud, Mentor Graphics
Area optimization and timing closure have long been considered the most common digital design challenges in mainstream digital IC design. Much has been analyzed and documented on how to solve these issues at the various design levels – from RTL to gate to layout. In recent times however, as design applications have become more portable and power sensitive, power exploration and smart design practices for optimizing power have taken centre stage.
Abstraction Facilitates Design Optimization
First, let’s review the benefits of high-level synthesis. As with the optimizations for area and timing, the earlier power challenges are tackled, the more flexibility the designer has for achieving an optimal solution. Now, with the availability of ANSI C++/next-generation high-level synthesis tools, power optimization can be approached more efficiently at a much higher level than RTL. [more]
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