Team SDR
Extreme Collaboration

Old wisdom says that too many cooks spoil the broth.  New wisdom says that accomplishing anything really big in high-tech requires a great deal of collaboration.  This week, new wisdom trumped old at the SDR forum as an unlikely coalition consisting of Texas Instruments, Xilinx, Green Hills, Objective  Interface, CRC, and even The MathWorks all had roles in producing a new platform for development of software defined radio (SDR) applications.

Software defined radio is developing into a benchmark challenge for the creators of technology.  The idea is simple enough – take the information coming in from an antenna and digitize it as early as possible.  Then, the entire behavior of the radio can be handled and modified in the digital domain with the flexibility of software.  Then (as the theory goes), hardware could be made very generic, and new radio standards could be quickly deployed and changed in the field without replacing hardware.  One radio could do the work of many with greatly reduced cost, improved operational flexibility and much greater security.

That’s all in theory, of course.  The reality is that huge technical barriers remain in the path of most design teams’ efforts to execute on that lofty vision.  Each piece of the SDR puzzle is a formidable problem, pushing the limits of technology and engineering resourcefulness.  The SDR challenge also spans a great number of disciplines, making a single-company, single-team solution almost infeasible. [more]

Computational Bottlenecks and Hardware Decisions for FPGAs
by Dave Strenski, Cray Inc.

The High Performance Computing (HPC) community recognized the inherent limits of serial processing long ago. In the drive to continually improve the performance of HPC codes, programmers have explored a variety of alternatives, including employing new types of processors, coupling multiple processors, and parallel processing. Initially, these strategies were hindered by slow inter-processor communications and limited ability to parallelize algorithms. As a result, early attempts at alternatives to serial computation could employ only tens of processors. Over time, several innovations (including higher-bandwidth inter-processor links, algorithmic improvements that reduced the amount of data sent across those links, coarse-grain parallelism, and the emergence of lower-cost microprocessors) allowed programmers to effectively employ hundreds of microprocessors. Current state-of-the-art systems can apply thousands of microprocessors with high-bandwidth, low-latency interconnects to the most challenging HPC problems. Nevertheless, even these systems have limitations for certain types of HPC applications. Eventually, the extra overhead required for parallel processing overcomes the benefits that the additional processors provide, and the performance gains that one would expect approach an asymptotic limit. [more]