a techfocus media publication :: October 31, 2006 :: volume XIII, no. 05

FROM THE EDITOR

Ever finish a complex design only to get that nagging feeling in the back of your head that something is wrong? Our Halloween feature article takes a gloomy glance at the dark side of digital design that keeps us all awake at night. Pleasant dreams!

In this week's Journal Forums question - we ask for your stories of phantom bugs - the ones that appear and then disappear - the ones that kept you up at night and taunted you. We want the bugs that showed up in the production system but not in the prototype, the ones that stopped when you connected the scope - the ones that happened in the regular executable, but not the debugger... Share the fear.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:
comments@fpgajournal.com. If you'd rather sound off in public, please post your comments or questions in our new Journal Forums.

Kevin Morris – Editor
FPGA and Structured ASIC Journal

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CURRENT FEATURE ARTICLES

The Haunting of Fab 51
An FPGA Designer's Nightmare
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JOURNAL WEBCASTS


The Haunting of Fab 51
An FPGA Designer's Nightmare

The wild wind whistles strange through the bright gloom of eternal daylight in the tightly-sealed semiconductor fab.  In the power-assured place where progress never pauses – where cryptically-coded wafers plod persistently through mysterious machines in the acrid vacuum of the clean room – where white-suited phantoms pass FPGAs through evil rays and deadly potions and spinning saws… something is amiss.

In the nooks and crannies of nanometer features – in the spaces between the spaces – in the places where the design rule checkers never checked, engineers never engineered, and vectors never ventured, there is a problem brewing.  It is a most subtle trouble - a fiendish flaw whose sinister scheme is carefully camouflaged in the vast microcosm of the die's twisted traces - hidden in the heavily doped spaces – dreaming of the twisted faces of the design engineer whose fear has come to pass, whose fate is sealed at last, whose time for action has passed.

In the cold confidence of the lab, these ghoulish gremlins will never surface.  They lurk in the LUTs with far greater purpose, biding their time until the day of reckoning and doom – lying in wait for the glory of their gloom, patiently seeking their accidental Igor, the hapless catalyst, the unwitting accomplice who unknowingly trips the wire and starts the reaction - unleashing the fire.

Step, step, step, step, click, whirr, click, step… the boats move along in their monotonous rhythm, micro-controlled mechanisms meticulously metering them on down the line - their haunted cargo just biding its time – their wafers just waiting – their fate not abating. Steely-eyed inspectors hover like specters, peering through microscopes, scanning for flaws.   Balls of hot solder melt and flow, melt and flow, melt and flow.  Shining saws strip sand from the die, dicing and carving, picking and placing, moving and packing, and everything's checked, and checked, and checked.

An ocean away, he awakes from his sleep –– a neuron of dread – some far-forgotten flaw that sticks in his head - a doubt.  He flashes a thought about something he missed, a bit not quite right that troubles his rest and ruins his night.  The months of hard work have exhausted his mind.  He struggles to find - an answer, a clue to his autumn-eve's dream.  He lies and he thinks.

He's labored for years on the details of design, carefully composing a silent symphony of silicon – a microscopic masterpiece of monumental proportions - a static array of unmatched kinetic capabilities.  His tables of truth are pictures of perfection, his logic cells arranged in the ideal locations - he's tested the flow on many occasions.  He's stared 'till he's blind at the eye that won't close while billions of bits scorch through rickety lines – his errors were counted, pre-emphasis mounted, and everything checked. And checked, and checked. [more]

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