Sensible SerDes at Sixty Five
Xilinx Launches LXT

At first, high speed serial I/O was a checkbox item in FPGAs – either you had it or you didn't. FPGA vendors bolted transceivers onto their devices, fired off some press releases, and let the games begin. As the race heated up, the competition became one of speed and versatility. FPGA transceiver complexity exploded as vendors vied to lay claim to the most standards and protocols supported, the highest bit rates, the lowest jitter, the highest jitter tolerance, and just about any other specification where a superlative could be claimed.

Of course, the more you try to do everything at once, the less likely you are to do anything well. As transceivers grew in complexity, compromises had to be made in areas like area, power consumption, and yield. Unlike ASIC- and structured-ASIC-based SerDes, transceivers could not be optimized for any particular speed or protocol. The transceiver was fabricated before the application was known, so FPGA-based SerDes transceivers became the Swiss Army knives of serial I/O.

Imagine, however, that you're shipping something like a Swiss Army knife, and you're having trouble getting something like the fingernail clipper attachment to work properly. Even though most of your customers don't care much about that feature, you're faced with a dilemma – you can't ship your product with a known defect. In semiconductor terms, you're faced with two choices – both of them bad. You can ship only those units where the clippers actually work, raising the cost for everyone. You could also try shipping the units with a disclaimer about the clipper functionality. Either way, your product becomes the victim of its own versatility.

Over the past year, we've been seeing the first major backlash against the do-all, end-all transceiver. Starting with Altera's Stratix II GX announcement, we saw for the first time a vendor who backed away from the temptation to go for superlatives over sensibility. Altera shipped their new family with a lower speed range than that already claimed by archrival Xilinx. In the tit-for-tat titanic marketing struggle between the two feuding FPGA vendors, it was an almost unthinkable move, but it paid off. Altera was able to build transceivers that were reliable and efficient at the target speeds of most of their customers, and they probably saved a bundle in the process. [more]