a techfocus media publication :: October 10, 2006 :: volume XIII, no. 02

FROM THE EDITOR

With the In-Stat Fall Microprocessor Forum in session this week in San Jose and a host of recent announcements around FPGA-based embedded computing, we’ve been thinking a lot about embedded processing with FPGAs. Our newest FPGA Journal FORUMS polling question is about your experience with processors on FPGAs. Have you used them? Did they work? Visit the poll and share your experience. (You’ll have to login to vote.)

Our first new feature article looks at Xilinx’s recent announcement of support for the MOST bus used in high-end automotive in-cabin systems. They’re rolling out a soup-to-nuts design kit to walk designers down the garden path for a very specific class of end applications. Is this focused, kit-based engineering and marketing just the tip of an emerging iceberg where vendors deliver a complex combination of shrink-wrapped silicon, IP, software, tools and services to entice designers into their camp?

Our second new article looks at a radical new architecture from Ambric that incorporates FPGA-like flexibility and parallelism with a device-specific structured programming model. Ambric’s aim was to shorten the path to teraflops performance for demanding algorithms like HD video encoding. We take a look at the new technology.


Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:

comments@fpgajournal.com.

Kevin Morris – Editor
FPGA and Structured ASIC Journal

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CURRENT FEATURE ARTICLES

Making the MOST
Xilinx Targets Telematics Bus
Power Parallelism
Ambric Accelerates Algorithms
It's All About Us
FPGA Journal Turns Three
Soft Core War
LatticeMico32 Opens the Field
Lattice Breaks the Rules
Slips SerDes into Low-Cost FPGA
Connecting the Camps
Mathworks Bridges System and Hardware Design
IP to Go
Chip Estimate Fills the IP Gap

JOURNAL WEBCASTS

UPCOMING WEBCASTS:

Embedded Design with LatticeMico32 Open,
Free 32-bit Soft Processor
sponsored by Lattice Semiconductor
Date: October 18, 2006
Time: 11am PST

Click here to register

ON DEMAND WEBCASTS:

Harnessing ModelSim Designer to Improve your FPGA Design Productivity


Optimizing Verilog Coding for More Efficient FPGA Synthesis

Designing 2Gbps Parallel I/O with the LatticeSC FPGA

Lattice's new 90nm LatticeSC family -- General Introduction


Making the MOST

Xilinx Targets Telematics Bus

In the good old days, people knew what a LUT was.

Why, when I was a design engineer, we taped out our design on glass – with real tape. There was none of this fancy new lithography. After FPGAs came out, we used to work out the LUT truth tables by hand, coding up Karnaugh maps to minimize our equations, doing De Morgan equivalents… Heck, kids these days with all their fancy IP blocks and algorithm compilers – they couldn't cross-couple a NAND gate if their life depended on it. Spoiled, I tell ya'!

Back in the day, FPGA designers were a determined bunch. They had to be. They needed the special advantages of FPGA technology so badly that they would practically walk across hot coals to get the darn things to work. Today, however, designers have two things that those engineers did not – schedule pressure, and options. With market windows closing almost before they've opened, you've got to get your design out into the world fast enough to avoid getting a finger chopped off. You don't have time to make a career learning the vagaries of one device or one technology. For any given electronic design problem, there are several compelling solutions competing for your socket, and you've got to pick one, use it, and move along without having to marry the technology. [more]


Power Parallelism
Ambric Accelerates Algorithms

Computing architectures have reached a critical juncture. The monolithic microprocessor has collided with the thermal wall with a resounding, "Ouch! That's too hot!" Traditional processor architects have moved on to dual-and-more core processors, pursuing some parallelism to mitigate their power problems. Other technologies have responded with "Hey, if parallelism is the solution, why not really go for it?" Compute acceleration with devices like FPGAs can boost the number of numbers crunched per second per Watt by orders of magnitude, but programming them is an activity akin to custom hardware design – hardly safe territory for the average software developer seeking to speed up his favorite algorithm.
[more]

EVENTS & ANNOUNCEMENTS

Seminar on Using FPGAs in Low Power Applications Hosted by Mentor Graphics and Quicklogic

Seminar attendees are eligible to win a Cruise for two to Alaska!

"Accurately Predicting and Simulating FPGA Power Levels to Reduce Power Consumption in System Designs" - San Jose, CA - October 11
More information and registration.

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