FROM
THE EDITOR
Overture, curtain, lights - this is it – the one and only third anniversary of the FPGA world's favorite publication. While there's no danger that our three candles will start a bonfire, we at FPGA Journal are extremely proud of the fire we've fueled in the FPGA industry over the past three years. Our latest feature is a modest (yeah, right!) and objective (maybe not so much) overview (self-aggrandizing chest beating is more like it) of our three year history. Hey, cool it, Parenthetical Honesty Man! We're trying to plug an article here… (sorry)
We'd also like to direct your attention to the new FPGA Journal FORUMS where you can comment (in public, even) on our articles, weigh in on polling questions, and kick around other topics of interest. We're starting things off with a poll on your favorite article of year three in FPGA Journal (See! More trolling for compliments…) We've narrowed it down to the top 10 based on number of reader comments, and now it's up to you to pick a winner. Don't fail to register and vote.
Finally, we've got many new and cool webcasts. Mosey over and check out the listings and register while you can. It's been an awesome year three here at FPGA Journal, but just wait until you see what we've got planned for year four.
Thanks for reading! If there's anything we can do to make our
publications more useful to you, please let us know at:
comments@fpgajournal.com.
Kevin Morris – Editor
FPGA and Structured ASIC Journal
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JOURNAL WEBCASTS
UPCOMING WEBCASTS:
Harnessing ModelSim Designer to Improve your FPGA Design Productivity
Sponsored by Mentor Graphics.
Date: Tuesday, October 10, 2006
Time: 9am PST
 Click here to register
Embedded Design with LatticeMico32 Open,
Free 32-bit Soft Processor
sponsored by Lattice Semiconductor
Date: October 18, 2006
Time: 11am PST
 Click here to register
ON DEMAND WEBCASTS:
Optimizing Verilog Coding for More Efficient FPGA Synthesis sponsored by Lattice Semiconductor
 Click to view now
Designing 2Gbps Parallel I/O with the LatticeSC FPGA
sponsored by Lattice Semiconductor
 Click to view now
Lattice's new 90nm LatticeSC family -- General Introduction, sponsored by Lattice Semiconductor.
 Click to view now
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It's All about Us
FPGA Journal Turns Three
Three years and over one-hundred-fifty editions ago, the first copy of FPGA Journal rolled off the virtual presses, coursing its way through the digital jungle to about a thousand unsuspecting initial subscribers. Our first feature article, "Making the Transition – FPGA Primer for ASIC Designers," was well received, as were most of the ninety-one features and hundreds of news stories we ran that first year in 2003 and 2004. If you've never browsed our [archives] section – it can be quite entertaining.
During our first three years, we've charted the changes, analyzed the trends, reported on the revolutions, and even documented the dubiousness of the most mesmerizing time in the young history of the programmable logic industry. From the beginning, we set out to be an engineer's publication, dedicated to the notion that engineering is an exciting, challenging, and rewarding occupation – believing that engineers are some of the most important contributors to our global society. We also understand that, even though we engineers tend to be technically minded, we don't deserve to be bored to death by dull dry technical diatribes droning on like dumbed-down datasheets. With that in mind, we try to make FPGA Journal articles not just informative but also entertaining, introspective, and even funny on occasion. [more]
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EVENTS & ANNOUNCEMENTS
Verifying Complex ASICs through FPGA-based Prototyping.
Learn how prototyping using advanced RTL partitioning
and RTL debugging tools helps you achieve predictable results with lower costs. The flow described in this paper is fully compatible with many of the off-the-shelf prototyping boards available from many board vendors.
 Click here to download the paper.
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Identify RTL Debugger - instrument and debug directly in RTL source code. The Identify RTL Debugger is a debug-centric verification tool which offers the fastest method of finding errors in a design by providing simulator-like visibility into a live, running FPGA.
 Click here for more info.
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