a techfocus media publication :: September 26, 2006 :: volume XII, no. 13

FROM THE EDITOR

This week, we have a new embedded processor to choose from.  Lattice Semiconductor has rolled out an open-source 32-bit RISC soft-core that is compatible with their lines of FPGAs, and could be extended to other platforms as well.  Our newest feature article takes a look at the new core and at the chess game currently going on in the FPGA system-on-chip race.  As FPGAs become more popular embedded processing platforms, we will be seeing more of these announcements as silicon and IP vendors battle it out for primo-processor honors.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:
comments@fpgajournal.com.

Kevin Morris – Editor
FPGA and Structured ASIC Journal

LATEST NEWS

September 26, 2006

Mentor Graphics Eases Software Development Tool Cost Issue with EDGE Development Suite

QuickLogic Launches Complete Programmable CE-ATA Solution at Intel Developer Forum

Parsec Announces PMC Module Leveraging Altera’s Stratix II GX and Stratix FPGAs

MorethanIP 10 Gigabit IP Solutions Ensure First-Pass Silicon for Astute Networks' Next Generation ASSP Advanced Storage Processors

Esmertec and MIPS Technologies Announce Optimal Java(TM) Solution on MIPS32(R) 24Kc(TM) Processor for Blu-ray Disc(TM) Products

September 25, 2006

Lattice Launches Ultra Low Cost Programmable Power Management Solution For High Volume Consumer Applications

Cypress Launches Fast Track™ University Alliance Program Featuring Global Design Competition, Web Resource Center, Product Donations and New-Hire Rotations

Rambus Showcases Silicon Verified Demo Compliant with Gen2 Revision 0.5 Specification for PCI Express

QuickLogic Adds DVD ROM Support to Its Programmable IDE Companion Device
The IDE Companion Device Provides Control and Interface Functionality for Mass Storage Adoption in Portable Electronics

MathStar, Inc. Announces the Second Generation of its Field Programmable Object Array(TM)

September 22, 2006

Xilinx Demonstrates Latest Programmable Solutions for Aerospace and Defense at MAPLD 2006

September 21, 2006

VMETRO SANbric stores flight test data

HARDI Electronics Provides ASIC Prototyping for Tensilica's Diamond Standard Processors

September 20, 2006

Tektronix and FS2 Collaborate on Real-Time Logic Debug Solution for Xilinx FPGAs

September 19, 2006

Micrium's Royalty-Free uC/TCP-IP Networking Stack Available for Free 45-Day Evaluation

eInfochips Becomes Authorized Tensilica Processor Design Center; eInfoChips Provides Proven SOC Design and Embedded Software Services for Tensilica Customers

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CURRENT FEATURE ARTICLES

Soft Core War
LatticeMico32 Opens the Field
Lattice Breaks the Rules
Slips SerDes into Low-Cost FPGA
Connecting the Camps
Mathworks Bridges System and Hardware Design
IP to Go
Chip Estimate Fills the IP Gap
Accelerating RTL Analysis & Creation with Spreadsheets
by Michael Lee, Mentor Graphics
Spartan-3 Goes Golfing
Axcon Drives TrackMan Radar

Flash Freeze
Actel’s Igloo Attacks Power

JOURNAL WEBCASTS

UPCOMING:

ModelSim Designer. A complete FPGA design environment at an entry-level price.
Date: Tuesday, October 10, 2006
Time: 9am PST

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ON DEMAND:

Optimizing Verilog Coding for More Efficient FPGA Synthesis sponsored by Lattice Semiconductor
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Designing 2Gbps Parallel I/O with the LatticeSC FPGA
sponsored by Lattice Semiconductor

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Lattice's new 90nm LatticeSC family -- General Introduction, sponsored by Lattice Semiconductor.
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Soft Core War

LatticeMico32 Opens the Field

In another of their trademark one-two punch announcement flurries, Lattice Semiconductor paired up their low-cost SerDes announcement we covered last week [SEE ARTICLE] with an announcement of a new 32-bit RISC processor core that is compatible with their range of both high-performance and value-based FPGA families. The new offering takes a different tack from previous FPGA-based processors, with a completely open use model for a proprietary soft-core processor. Lattice ’s strategy could help level the playing field in the odd array of offerings currently available to design teams creating FPGA-based systems-on-chip (SoCs).

Before FPGAs became viable system-on-chip platforms, there were two simple basic food groups in the embedded processor world: stand-alone processors for board- and module-level integration and processor IP cores for system-on-chip integration. Some of the most successful offerings today are processor architectures that managed to span both of those domains, such as ARM ’s wildly successful architectures that have attained widespread adoption both as flexible IP cores in ASIC SoC implementations and in high-value, stand-alone chipsets for board-level integration.

Recently (as we’ve thoroughly documented in these pages), FPGAs have shrunk and grown to the point that they, too, are viable options for system-level integration. When we hit the point that an FPGA could house a reasonable 32-bit processor capable of running an OS or RTOS, enough peripherals to construct a useful machine, and enough memory to run an interesting application, we entered a new era of embedded processing options.

The situation with FPGA-based processors is unique, however, with several factors separating the new environment from the existing mainstream. First, early attempts at embedding hard processing elements in FPGA families failed, as none of the players managed to mix a chip that offered on-chip processing power matching what could be added externally for less money. Soft-core processors tended to be preferred because of their greater degree of flexibility and because they didn’t increase the cost of devices for applications where a processor was not needed. [more]

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