a techfocus media publication :: September 19, 2006 :: volume XII, no. 12

FROM THE EDITOR

This week, Lattice Semiconductor continues their two-year parade of disruptive announcements with a new FPGA family that bundles SerDes capability, large amounts of memory, and high-performance DSP blocks into a low-cost FPGA. Officially, we're shocked - that sort of thing goes against all the unwritten rules of polite FPGA competition. Unofficially, we think it's pretty cool - what is "polite" FPGA competition anyway?

Our second new feature looks at the latest release from The MathWorks - a new product called Simulink HDL Coder. On the surface, HDL Coder is a potential breakthrough product - bridging the gap between the system design world of MATLAB and Simulink, and the deep-tech implementation world of HDL hardware design. Below the surface, however, is an incursion of sorts. With this announcement, The MathWorks puts an undisputed foot (not just a toe or pinky) in the EDA sandbox. The results will be interesting to watch.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:
comments@fpgajournal.com.

Kevin Morris – Editor
FPGA and Structured ASIC Journal

EVENTS & ANNOUNCEMENTS

Get Your Complete Xilinx Development Board Solution!
An Incredible Value at $149 - Xilinx Spartan™-3E FPGA Starter Kit gives you instant access to capabilities of the Spartan-3E family. Kit includes board, power supply, evaluation software, resource CD, and USB cable.

Order your kit today!

CURRENT FEATURE ARTICLES

Lattice Breaks the Rules
Slips SerDes into Low-Cost FPGA
Connecting the Camps
Mathworks Bridges System and Hardware Design
IP to Go
Chip Estimate Fills the IP Gap
Accelerating RTL Analysis & Creation with Spreadsheets
by Michael Lee, Mentor Graphics
Spartan-3 Goes Golfing
Axcon Drives TrackMan Radar

Flash Freeze
Actel’s Igloo Attacks Power

Bit-Based Dynamic Alignment for Multi-Gigabit Parallel I/O
by Ron Warner, Lattice Semiconductor Corp.

A Mile in Their Shoes
Altium’s Engineering Empathy

JOURNAL WEBCASTS

UPCOMING:

ModelSim Designer. A complete FPGA design environment at an entry-level price.
Date: Tuesday, October 10, 2006
Time: 9am PST

Click here to register

ON DEMAND:

Optimizing Verilog Coding for More Efficient FPGA Synthesis sponsored by Lattice Semiconductor
Click to view now

Designing 2Gbps Parallel I/O with the LatticeSC FPGA
sponsored by Lattice Semiconductor

Click to view now

Lattice's new 90nm LatticeSC family -- General Introduction, sponsored by Lattice Semiconductor.
Click to view now


Lattice Breaks the Rules

Slips SerDes into Low-Cost FPGA

FPGAs fall into two distinct camps – high-performance and low-cost. For several years, the rules and conventions of these strata have been established and followed by FPGA companies. Low-cost or value-based FPGAs are designed with cost as the first priority. Every spare feature is thrown overboard in order to minimize die size and production cost, leading to the lowest possible price-per-LUT for a given amount of programmable fabric. High-end FPGAs, on the other hand, spare no expense in offering the maximum performance and the richest feature sets.

The silicon selection rules for FPGA designers have been, therefore, rather easy to understand. If you have a high-volume, cost-sensitive application, you go for the value-based FPGA. If you need advanced features like DSP blocks, super-fast clock speeds, and the queen of all high-end features – SerDes transceivers, you popped out the checkbook and went for the exotic high-performance families. It was unambiguous. You were in either group A or group B. There was no middle ground. [more]


Connecting the Camps
Mathworks Bridges System and Hardware Design

It happens from time to time. Some well-meaning high-tech company notices that they've got some pretty cool design tool technology and says to themselves, "Hey, we've got some cool design tool technology. Let's jump into the EDA market! " These are fateful thoughts, however - best pushed aside. In practical terms, they are akin to "Hey, I've got myself a pretty cool racing bike – I think I'll compete in the Tour de France!" Sometimes, though, a company that, perhaps, developed some nice tools for their own internal use, feels just too tempted and takes that ill-advised plunge. The results are typically disastrous. These adventurers usually soon discover that creating tool technology is the easy part. Getting electronic designers to adopt and depend on your software, regardless of how novel and necessary it may seem, is a much more daunting challenge.

The MathWorks is bucking that trend, however, because they've approached the problem from a different direction. First, they won the hearts and minds of the electronic design community with their general purpose (non-EDA-specific) tools like MATLAB and Simulink. Then, when they apparently noticed that they had thousands of seats of software in places where only EDA companies typically played, they set about developing domain-specific technology to try and capitalize on that market presence.
[more]


Visit Techfocus Media


You're receiving this newsletter because you subscribed at our web site www.fpgajournal.com.
If someone forwarded this newsletter to you and you'd like to receive your own free subscription, go to: www.fpgajournal.com/update.
If at any time, you would like to unsubscribe, click here. (But we hope you don't.)
If you have any questions or comments, send them to comments@fpgajournal.com.

All material copyright © 2003-2006 techfocus media, inc. All rights reserved.
Privacy Statement